FPGA Project Daily Software Development Mangement

[K.Waris]

I have noticed that every day when I finish work on project and take a copy of this project and rename it to be used the next day and open the FPGA vi from the new project folder, Xilinx starts compiling FPGA VI again. Is there a method that I could manage my everyday work so the next day I open the FPGA VI from new folder, it wont ask for another compile?

Kind Regards

Austin

[RER · Accepted solution]

Hi Austin,

I replicated the issue using the following steps.

1) Create a folder and save a new a project inside
2) create an FPGA target in the project

3) create a simple FPGA VI under the target
4) create a build specification for the FPGA and compile it.
(note the name automatically generated for the bitfile)

5*) copy the folder with everything inside it (project file, FPGA VI, bitfile, aliases, etc..) to another folder
6*) try to run the freshly copied VI directly under the FPGA target (it will start to compile)

Reason: The name of the bitfile you specify (in the build specification) has changed to a new name that didn't exist before, so LabVIEW tries compiles it again.

Here is my build spec of the original project...

Here are the build specs of the copied project...

If you replace steps 5 & 6 with the following 2 steps, it seems to prevent the recompile.

5*) copy the original folder again with everything inside it
6*) this time, change the name of the bitfile in the copied build specification to be the same as the original bitfile name (see step 4)
Run the FPGA VI and you'll notice that you won't need to recompile this time.

Thanks for your time,

[K.Waris]

Spot On!