FPGA SCTL Throughput and ready for input management

[Rufnek]

I've studied the Normalize vector LV FPGA examples and I have a question about the ready for input wire (see attachment for the diagram).

A subVI (named ReadyForInputLogic) is use to generate a ready for input signal  to TRUE every 7 cycles after each valid input.

I well understand the goal of this subVI but, is the subVI can be replaced by a wire between the "ready for input" output of the last divide block and the case diagram where the FIFO is read ? 

I also studied the FFT Co-processing example and there is no need to use this kind oh subVI :

I've modified this example to add some multiply and divide blocks after the FFT block. So, the new whole throughput is increased to 8 cycles/sample (the FFT block is not the bottleneck).

Do I need to add the ReadyForInputLogic.vi subVI in my SCTL to read the FIFO every 8 cycles ?

Many thanks for any explanation

[BillMe]

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@Rufnek wrote:

I well understand the goal of this subVI but, is the subVI can be replaced by a wire between the "ready for input" output of the last divide block and the case diagram where the FIFO is read ? 

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Yes you can but then you run the risk of dropping a result when the write to the FIFO fails because it is full. The logic is currently setup to stop processing vectors until the FIFO is not full.

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@Rufnek wrote:

I've modified this example to add some multiply and divide blocks after the FFT block. So, the new whole throughput is increased to 8 cycles/sample (the FFT block is not the bottleneck).

Do I need to add the ReadyForInputLogic.vi subVI in my SCTL to read the FIFO every 8 cycles ?

Many thanks for any explanation

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You need to add up the latencies to determine how often you can read the FIFO. The FFT as setup in that example has a latency of >5600 cycles before the output is valid.

[BillMe · Accepted solution]

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@BillMe wrote:

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@Rufnek wrote:

I well understand the goal of this subVI but, is the subVI can be replaced by a wire between the "ready for input" output of the last divide block and the case diagram where the FIFO is read ? 

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Yes you can but then you run the risk of dropping a result when the write to the FIFO fails because it is full. The logic is currently setup to stop processing vectors until the FIFO is not full.

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@Rufnek wrote:

I've modified this example to add some multiply and divide blocks after the FFT block. So, the new whole throughput is increased to 8 cycles/sample (the FFT block is not the bottleneck).

Do I need to add the ReadyForInputLogic.vi subVI in my SCTL to read the FIFO every 8 cycles ?

Many thanks for any explanation

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You need to add up the latencies to determine how often you can read the FIFO. The FFT as setup in that example has a latency of >5600 cycles before the output is valid.

I would say yes, since the FIFO will be ready for a new sample before your math blocks.

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[Rufnek]

Thank you for your answers. I think that I have to modify the VI's architecture.

I will try to remove some divide blocks in order to get to increase the FFT SCTL throughput. Like this, the FFT block will be the bottleneck.

The FFT post-processing blocks will be placed in an another SCTL. My FPGA VI will have 2 SCTL :

1 : FFT SCTL, which is processing the FFT + scaling factor

2 : Post FFT processing, in order to calculate the Magnitude and send it to the Host

I will post a new message when it will be ok !

Thanks,

Regards

[Rufnek]

I'm sorry for my delayed answer but this is good working. Many thanks for your help !

Regards,