FPGA - Serial TTL

[DailyDose]

Hello LabVIEW community.  I am currently trying to use a 9870 to talk RS232 via FPGA.  This appears to be more difficult than expected with methods and what not.  There's various forums and a couple white papers and 1 example.  So I'm doing my homework learning to run this.

But a discussion came up.  What if I used a TTL DO module and ran it to a RS232 converter.  I thought about that.  That wouldn't be impossible.  But slightly tedious.  I was curious if LabVIEW community knew of a pre-existing VI/API that uh... would speed up this development process.

[deceased]

To make your own serial using something like a 9401 TTL Digital module, then level shift, is very much possible. It would be a hell of a lot more work, since you are now concerned with the intra bit timings etc.

I used to roll my own serial code in assembly on microcontrollers that didn't have UARTS and its not a pleasurable experience overall.

I have used the 9871 (rs485) in FPGA in one of my systems and it works very well. I suspect the rs232 version operates the same way,

What exactly is it you are struggling with?

0xDEAD

[Ben]

This PDF looks like it may help out.

Spoiler

Please do not learn anything about code style when looking at that pdf.

Ben

[DailyDose]

The issue was isolation.  Just a few more components required on a custom board to isolate all 232 communications.  Requires we change it to TTL, isolate it, then TTL back to 232.  So the discussion was, use a DO card to send serial via TTL and have one less conversion.

The PDF offered is about what I had expected to do in terms of functionality except more refined of course.  The real trick would be listening and interpreting.  I guess it wouldn't be too hard.  Just more work.

[DailyDose]

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@Ben wrote:

Spoiler

Please do not learn anything about code style when looking at that pdf.

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Also, I didn't see this part until after I had read the PDF.  I was thinking the entire time... is this really recommended style for this?  I would thin FOR loops would easily be WAY more efficient.  Then I saw this spoiler.  So... .whoooo. lol

[deceased]

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@DailyDose wrote:

The issue was isolation.  Just a few more components required on a custom board to isolate all 232 communications.  Requires we change it to TTL, isolate it, then TTL back to 232.  So the discussion was, use a DO card to send serial via TTL and have one less conversion.

The PDF offered is about what I had expected to do in terms of functionality except more refined of course.  The real trick would be listening and interpreting.  I guess it wouldn't be too hard.  Just more work.

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Out of interest what cRIO/sbRIO are you using? Does the RT component need to send/receive the messages (via the FPGA) or only the FPGA?

If the RT how many DMA FIFOs are you currently using?

0xDEAD

[DailyDose]

We're using a NI 9149.  This is a ethernet FPGA device.  I would love to just use VISA on the RT, but that's not an option with this.

[deceased]

Ahhh, you see where I was going with that. When them modules where first released they only supported FPGA mode but I think since 2010 you can put a CRIO in hybrid mode and use NI Serial too. This instantly steals 2 DMA FIFO channels though, so not always a great idea.

[DailyDose]

So just to make sure, Scan Engine is completely out of the question?

[deceased]

I'm not sure if the 9149 supports it, I have never used an Ethernet RIO. 

If it does support scan engine it might be exactly what you need.

0xDEAD