FPGA Simulation Test Bench

[Worle]

I have recently discovered the ability to simulate FPGA's with a custom test bench.

This is almost useful to my workflow.

My main issue with it is the necessity to create a string controlled case for every IO node. Whilst doable it is a bit of a pain because really I just want to control a couple. All the others can be random values/set to 0. 

My thinking was that  on first call I can programmatically get all of the FPGA IO nodes and get their data types. I then have a bit of code which generates random data for an input variant. I could put this in the default case of my test bench and then create seperate cases for the nodes I actually want to control.

I don't seem to be able to get this code to work though. It works fine for output nodes, it just doesn't work for inputs. (The map is meant to be a map of terminal names to terminal data types). Does anyone have any suggestions?

[Terry_ALE · Accepted solution]

The big time sink in FPGA development is the compile time.  I never automate what you mention because even with a lot of IO and controls/indicators it is not the part that slows me down.  My suggestion is to make test benches that manually test and then look for this kind of automation.

How many IO nodes do you have in your project?

[Worle]

I came to the same conclusion. It wasn't as painful as I first thought it was going to be.

I just always shy away from having string controlled case structures.