FPGA Sine Wave Generator timebase?

[Photon_Dan]

I think there is some hidden magic going on, and I'd like to see if anyone can help me peer behind the curtain.

Using the Sine Wave Generator VI in LabVIEW FPGA, I am able to produce nice sine waves on my analog outputs.  However, I have a requirement to vary the frequency, amplitude, and offset of my sine waves without disturbing the phase.  The amplitude and offsets do not mess up the phase, but changing the frequency on the fly does.  So, I decided that it's time to do the Open Front Panel on that Sine Wave Generator Express VI.  When I dig down in the code and strip away the unnecessary interpolation and cosine generation, I am left with a fairly simple looking loop.

OK, I understand all of that.  But, here's where I get lost.  I run the unmodified Sine Wave Generator in a loop on my FPGA target and I can see sine waves that are of my desired frequency, but the loop is not single cycle.  In fact it takes 366 ticks per cycle.  The code that I see when I Open the Front Panel looks like it depends on a 40MHz clock, but my loop is not running that fast.  So why are my sine waves still OK?

My theory is that when we Open Front Panel on that Express VI, we loose some extra code that is monitoring the actual loop rate.  The big scary warning message at the top of that diagram is a big clue.  I guess I'm just looking for confirmation of that, and if possible an example that includes the loop time compensation.

Thanks,

Dan

[srm@viewpointusa.com]

you are correct.  the unmodified version of the code compensates for the actual execution time behind the scene.  You can code your own equivalent but you need to either compensate for the actual loop rate or design it to run at a specific loop rate.

however it is easy enough to just vary the frequency of the built in generator by computing your own increment value corrosponding to new frequency.  the output will not have discontinuities.  you have to look at the equation for how to compute the increment value as a function of your desired frequency.  I have it somewhere, just not right here.

[JLewis]

Hi Dan,

The Sine Wave Generator can be thought of as an accessor to a free-running DDS (Direct Digital Synthesis) engine that does indeed run at the FPGA clock rate under the hood. The node itself just grabs the latest output from the engine each time it executes in the G dataflow environment. The LabVIEW code you're looking at under the VI is used only for desktop execution and is ignored during the FPGA compile process. Check the online help for tweaks to make the emulation behavior match what you'd see on the FPGA.

If we were creating this guy today we'd probably use an API more like the VI-Defined Memory, where you would have a free-standing node (or project item) representing the engine, and the sine wave data would be accessed via a Get Sine Sample method node or something of that nature.

Jim