FPGA Target to Host data transfer from 2 loops with different speeds

[JScherer]

I have two loops in my FPGA, one FIFO one runs at 100kHz and the other at 250kHz . What is the most effective way to transfer the data gathered in each loop from the FPGA host to the target? 

How should I write my Reading vi to ensure that neither FIFO fills with data?

Related:
https://forums.ni.com/t5/LabVIEW/FPGA-Write-Read-DMA-FIFO-for-multiple-channels-FOR-loop-vs/td-p/386...

[GerdW]

Hi JScherer,

use two loops in the host - you also use two loops in the FPGA…

[JScherer]

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@GerdW wrote:

Hi JScherer,

use two loops in the host - you also use two loops in the FPGA…

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I really should have thought of that... Unfortunately, It would be best for my code base if I could keep this in one ReadFPGA.vi . Is there a way to read both in one loop?

[GerdW]

Hi JScherer,

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@JScherer wrote:

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Is there a way to read both in one loop?

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Yes, sure.

Read 10k samples from slower FIFO and 25kS from faster FIFO!

(I'm unsure about any side effects. Check FIFO buffer fill rate for safety…)

[Terry_ALE]

I too recommend two separate VIs.  It keeps the two processes separate and I think it is easier in the long run in case changes are needed or if one needs to pause/stop and the other does not.

If you must however, on the host you would read the values available to read (from each FIFO), send to feedback node and read that many back on the next iteration.