FPGA Timing Error When Compiling PID Loop

[nathand]

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Orel Bechler wrote:

I would think that each tick would now stand for one 40 MHz cycle (which is 25 ns).  Is that correct?

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Yes, that's right.

[BruceAmmons]

I had the same problem with the FPGA PID vi.  I thought it was due to a few minor changes I made to the code, but it could be the original code.

The way to solve it is to convert the Express vi to a regular vi so you can edit it.  Create a 30 MHz clock.  Inside the PID code you will find a Timed Loop.  Change the clock for that loop to the new 30 MHz clock.  Problem fixed.

Bruce

[orelb]

Thanks for the tip, Bruce.

That could definitely come in handy...  but there's probably no way to set it up as a subvi so that it runs at 80 MHz...  right?

[BruceAmmons]

No way for it to work at 80 MHz.  The vi is currently set up to run through the SCTL loop three times at 40 MHz for each PID.  I think the timing is tight each time through the loop, which is why reducing the speed to 30 MHz fixes the problem..

The only way to get 80 MHz would be to write your own PID, if it was a simple version.  Even then, it would be difficult.  You really can't get much done in a single cycle at 80 MHz.

Bruce

[orelb]

Yeah that's what I figured...
You learn something new every day...

One last issue that still confuses me- what is a derived clock? If the clockrate of the FPGA is 40 MHz, how can it run at 80 MHz with the same accuracy? I read somewhere that a 200 MHz clock can also be derived. Is that true? How accurate will that be?

Thanks for your time.

[nathand]

The details of FPGAs are not my area of expertise, but I was curious and did some web searching.  There appear to be two common ways to generate a higher-frequency clock: a PLL (Phase-Locked Loop), or a DLL (Delay-Locked Loop).  A quick web search turned up a useful introduction from an FPGA vendor: http://www.altera.com/support/devices/pll_clock/basics/pll-basics.html.  There's also an application note from Xilinx about Digital Clock Managers (I'm lost after the first few pages, but it does provide an idea of what clock manipulation is possible).  The specifications for the FPGA board includes values for frequency-dependent jitter, which I think will answer your question about derived clock accuracy.

Fortunately LabVIEW simplifies the low-level FPGA details, but if you're interested in FPGA clocks and timing, this article seems like a good start: http://eetimes.com/design/embedded/4024526/FPGA-Clock-Schemes