FPGA VI runs in Emulation, but compiled, the result is wrong

[P. Horn]

Helo,

I am working with NI PXI-1042 rack with NI PXI-7813R FPGA I/O card.

I can run successfully RunFPGA BM+3_SCTL_3(FPGA).vi to generate dedicated PWM pulses, if only one FIFO is used in While Loop.

But I need 20 cycles to calculate new pulse generation.

Trying to make the calculation more simple and using the Emulation, Radar_3_EMU(FPGA).vi runs correct in the Emulation mode.

Compiled and loaded to the FPGA as Radar_3(FPGA).vi the output puses are wrong and it looks like that only one PWM cycle comes to the output.

Am I correct with following assumptions?

1) The FIFO Write function does not wait ewen if the Timeout is set to -1?

2) The Emulator does ticks for all loops after each other by making only one step i each loop. In the reality all steps are done in each Sinle-Cycle Time Loop but only few in the While Loops?

Are there any rules to calculate how many cycles are needed in a While Loop inside of the FPGA?

However my biggest problem is while the Radar_3(FPGA).vi does not function properly.

Peter Horn

[Marco_Brauner]

Hi Peter,

You have to consider the following points:

1.)  One cycle of a loop takes as many ticks as the sum of all ticks of the longest path in that loop is

2.)  You can use derived clocks to achieve a timing greater thatn 40 MHz

3.)  Putting a function in a loop which takes more than one tick destroys your timing scheme if it is supposed to be 

      one tick per cycle.

 concerning your questions:

1.)  The FIFO Write waits until the data is available and then writes it if timeout is -1

       For instance timeout = 0 wouldn´t wait and most likely throw an underflow error because of lacking data

2.)  I´m sorry, please explain again because I´m not able to understand that point clearly.

3.)  There are too many possibilities to generalize the question, but you can always just benchmark or measure the timings.

       I found a excel file listing the tick counts of some groups of functions (attached)

I`ve also attached a demo for PWM generation which you could use as a starting point or to copy some approaches.

[P. Horn]

Thank you Hans Your excel list was very surprising to me, because I did not expect that FIFO Read takes 2 cycles. There was originally suggestion from NI to write to FIFO a stream of PWM signals to a SCTL (Single-Cycle Time Loop) which will read the signal stream and just set the output depending on the reading from FIFO. If this is true I will use a memory stack, read and write pointers to do the arbitration instead of a FIFO. I will look at you PWM project tomorrow in the office. More explanation to the point 2): If you need numerically to debug the FPGA.vi using the Emulator, you can do it step by step. The emulator functions in the way that one step is done in a While Loop and the next one in the SCTL, if you have for example only these 2 Loops. In the reality it is expected that in a correctly running SCTL all steps are done within one cycle. Just as a hint to NI to improve the FPGA Emulator. Also using your list some information could be displayed about the cycle count.  How have you generated this Excel sheet?  It would be useful to bring error messages from the Compiler, if inside a programmed SCTL some actions could not be done within one cycle. I was using FIFO Read inside the SCTL, but no error has been reported.