FPGA asks me to compile code I have already compiled.

[Engbrecht]

I am writing code for my CRIO FPGA.  When I compile the code I want to use, usually it works fine.  However, at times the code will not run and suggests to me I need to compile code I have just compiled.  I seem to be able to fix this by changing the nature of my code or subtracting parts of it.  I have not, however, yet figured out exactly what it is in my code that is causing this.  On one occasion, disconnecting a single indicator seem to address the problem, however, that same indicator can be used elsewhere without problem.  I recieve no errors when I compile, but when it is completed it acts as thought the code were not compiled.

Any thoughts on things I might try to trouble shoot?

Jason

[Pcorcs]

Hi Jason,

What versions of LabVIEW, LabVIEW Real-Time, LabVIEW FPGA, and NI-RIO are being used? 

Also every time the code launches the compile server is the a 'Dot' next to the VI name? Does the code ever fail compilation? If you right-click the VI, and select 'Reconnect to compilation' can you successfully run the code without re-compile? 

Hopefully these questions will give you a few places to start. Please post back your results, and any further questions.

Cheers!

[Engbrecht]

Thanks for the suggestions. I don't have a solution yet, but I have a pretty specific example of the problem that might help.  

What versions of LabVIEW, LabVIEW Real-Time, LabVIEW FPGA, and NI-RIO are being used? 

NI-RIO is 3.1 All others are 8.6.1

Also every time the code launches the compile server is the a 'Dot' next to the VI name?

I haven't seen this though I'm not sure I understand what/where I am looking for.

Does the code ever fail compilation?

I would have said no, but it just did for the first time.

If you right-click the VI, and select 'Reconnect to compilation' can you successfully run the code without re-compile? 

No, it recompiles.

The most recent incidents seems to shed a little light on the problem though I still don't have a solution.  A sub-vi in the code had two outputs which were both multiplied by a constant before going to the output.  I can remove either or both of the multiplications and it works fine.  However, if I try to do both of the multiplications, I get the error I have described.  In other words, the problem does not seem to be a particular mistake in the code as all parts work fine.  Maybe I am pushing the size of the code.  This would be bit surprising to me.  How can I check for something like that.

 Thanks for the help.

[Pcorcs]

So,

The 'Dot', on the forums sometimes referred to as the 'Dirty Dot,' is a star in the title bar of the VI indicating that an object has been changed since that last known save of the VI. In FPGA programs, the 'Dot' inevitably leads to a required recompile. This dot can be induced by something as simple as moving object location on the front panel or block diagram, or modifying properties in the project explorer with respect to the FPGA target. 

In so far as removing multipliers changes the compilation behavior, FPGAs have a limited number of multipliers on the hardware circuitry. To review your device utilization, you may review the Xflow log file generated during a successful compilation. Toward the bottom of the log, you should see an outline of FPGA device utilization. This file is stored on XP machines:

c:/NIFPGAXXXX/SrvrTmp/localhost/[Your Application Folder]/XFlow.log

You should be able to open the log with Notepad. You will see something like this:

 

Please post back any additional questions.

[Engbrecht]

THATS the dot you mean.  I've been programming in Labview for a decade and I didn't know it was called that.  

Well I seem to have made progress.  On a recent failed compile the error was a timing conflict.  So I slowed down a loop and we seem to be doing better.  I'm still not sure why this showed up in the way it did, seemingly compiling but then acting as thought it hadn't, but it's working now so I can be happy with that.  Thanks for the help.