FPGA cloud compile at third party

[Harlequinade]

On the youtube video the FPGA compile farm and cloud compile are well explained (http://www.youtube.com/watch?v=LNKdpD2zaYE). I was wondering, at 6:15 it is mentioned to be able to use Microsoft, Google, Amazon and The Rackspace Cloud.

Would that be implemented in on of the coming patches, to submit the work to one of these companies with a user account and let it compile there and 1 minute later you get your bitfile back?

[falkpl]

I was under the impression that the FPGA compiler is still single threaded (once the compiler becomes parallel things could get interesting) so your bitfile would not be generated in 1 minute, but it will free up your local machine to continue work while your compile is being worked on in the cloud.  It can be compiled with different optomizations settings in parallel probably though.  This was my impression on the service.  A bitfile in 1 minute would be nice but I dont think the cloud solution promises this.

[Harlequinade]

My impression was that the whole FPGA bitfile compilation is searching to a global minimum for the bitfile, which means that it performs several iterations. That's also why when you recompile and nothing has changed, you still get different speeds. 

What I expected was that this finding of the global minimum for the bitfile can be made parallel.

From: http://zone.ni.com/devzone/cda/tut/p/id/11573

"As you can imagine, the mathematics behind finding a globally optimized solution to a problem that has infinite possibilities is, [...], “nontrivial.”"

[ernestm]

@falkpl is correct; in its first iteration the FPGA Compile Cloud service is just executing your compile in an optimized cloud environment - the xilinx compiles aren't parallelizable yet so they can't be broken up over a wide array for superfast processing map/reduce style at the moment.  It should be faster than compiling locally, but at the moment it's not an order-of-magnitude difference.

[falkpl]

even parallel at the first step is nice since you can compile for speed and also for minimum footprint.  you will get the faster compile back first by the time you validate that the logic is correct you will have a more footprint optomized code.  you will also beable to run a compile, make an adjustment to the code (lets say you are nut sure if you have to invert a single logic gate to get the correct logic output) queue up the second compile and get both back to try, this can save a lot of time.

I like the idea of a 1 min compile though.

[Harlequinade]

@mxyzplk that would be indeed nice if the compiler compiles more than necessary but gives you the one optimized for speed or space etcetera and you can choose ...

By the way, nice reading material: http://www.eetimes.com/design/automotive-design/4018460/Reducing-FPGA-Compile-Time-Using-Parallel-Co...