FPGA: compilation data stream

[dan_u]

Recently, after adding some more code to the FPGA design, I consistently get the message "A problem occured with the compilation data stream. The compilation will continue, but compilation reports will not be available until it is complete". This message appears 15-40 minutes after starting the compilation, and before the estimated device utilization report is available.

As the message states, the compilation continues, but when it finishes the estimated device utilization is not available. See screenshots.

This is annoying since the compilation takes ~2h and based on the estimated timing report I could decide to cancel the compilation or let it run. The design is quite at the limits regarding timings, we have code running at 200MHz and the compilation fails about 50% of the time due to timing violations. Now that I don't see the estimated timing report I always have to wait the full 2h.

Any ideas or suggestions?

Using LV2012 SP1 with Xilinx Tools 13.4 on a PXIe-7965R card.

[Elli · Accepted solution]

Hey Dan,

this is actually a Bug in this version. It has been fixed in the follow up versions.

So in order to see your estimated device utilisation you would need to upgrade your fpga module and Labview.

Or you try to optimize your code. When it's not running on the edge then this problem does not show up I guess.

Here some documentation on code optimization:

Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining

http://www.ni.com/white-paper/3749/en/

regards, Elli

[dan_u]

Hi Elli,

Thanks for the reply. Upgrading LabVIEW is not an option currently since we have dozens of systems in the field.

The design is optimized to the best of our knowledge, but there's certainly potential for further optimizations. But when adding more code (which we need to) we'll run into this issue again.