FPGA compile fails No Listeners on the GPIB.

[token96]

Hi, I'm trying to compile an FPGA file but every time I try,  the generating intermediate files step failes and shows the following error:

Error 2 occurred at an unidentified location  Possible reason(s):  LabVIEW:  Memory is full. ========================= NI-488:  No Listeners on the GPIB.   Method Name: <b>Generate VHDL</b>

any seggestions?

Additional Info:

LabVIEW Version: 2010.

FPGA type: FlexRIO PXIe-7965R

Windows 7: 32bit 4 GB ram and 8 GB virtual memory

[GerdW]

Hi token,

the error says: "Possible reason(s):  LabVIEW:  Memory is full." That's it...

[danil33]

Hi token,

              To  get exact source of the error, make sure you wire the error cluster throughout your code. Have you tried monitoring memory usage in Task Manager to see if the memory full error you are getting is correct?Better post your VI so that we can check it to see if there's any continuous memory allocation problems.

[GregFreeman]

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@danil33 wrote:

Hi token,

              To  get exact source of the error, make sure you wire the error cluster throughout your code. Have you tried monitoring memory usage in Task Manager to see if the memory full error you are getting is correct?Better post your VI so that we can check it to see if there's any continuous memory allocation problems.

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Danil, be careful when you are commenting on something, Your response is way off base. The error he is getting is while the FPGA is compiling, not during run time. This is an error the compiler is showing, not an error he is getting in his code. Furthermore, you cannot view FPGA memory usage in the task manager, even if you wanted to. Have you had experience with FPGA programming before? Make sure you are familiar with what you are responding to. I try not to respond to anything I haven't done before because I don't want to lead the poster off chasing something that may not be the issue.

To the OP:

Gerd is correct in saying the memory is full. What FPGA is being used? Is it possible to post your code so people here could help you make it more efficient? When buying your FPGA, did you spec it out of the amount of data you would be acquiring and needing to buffer to make sure it could do what you needed it to? Often times when I have run into this error I am trying to make my FIFOs hold too many elements, and I need to reduce that and read from the FIFO faster on the RT.

edit: I just saw you posted your RIO type

[token96]

Ok, do you have any suggestions for this problem?

[GregFreeman]

Basically it means the code you are trying to put on the fpga is too big for the fpga. Without seeing the code I can't make any suggestions. Make sure there isn't any processing on the fpga that could be done in the RT. Make sure your FIFOs are not requiring large amounts of memory. Again, these are just guesses, without seeing the code it isn't really possible for me (or anyone)to know.