FPGA compiling- Timing violation Error

[thutch79]

Hi all,

I've been around LV for years now, but I'm a complete newbie when it comes to FPGA. I'm working on programming for a 9651 (SOM) using the Dev kit. I'm starting with baby steps, but already tripping up. I have a simple VI that grabs a value from a FIFO and passes it back out to another FIFO. Upon compiling, it's giving a timing violation error and I don't know how to investigate it. Attached is the VI.

So background for the curious... I'm working on the signal processing side of our application. I'm passing data from a pre-recorded TDMS file to a FIFO. I want to send it to the FPGA, process it, and send it back. Eventually this will come from I/O, but for now, I just want to work on the signal processing. Before even starting the work, I figured I'd just make sure I can pass data down and back. Once I get that working, I'll start developing the processing VIs for in between.

Thanks!

[Spex · Accepted solution]

Hi thutch79,

Can you detail the version of LabVIEW you are using and the socketed CLIP implementation you are using for the DevKit IO?

There was a timing violation introduced between LabVIEW 2014 and 2015 because of the way the Xilinx compiler handled the VHDL that supports the second Ethernet port on the SOM.  If you use a socketed CLIP that was generated prior to LabVIEW 2015 (like the shipping example which I believe starts with a CLIP called "DevKit"), then you can get a timing error.  There should be a second example CLIP called DevKit2, I believe, which was regenerated with compatibility for LabVIEW 2015 and later.

This behavior was discussed here: https://decibel.ni.com/content/thread/42711

You can check your socketed CLIP in the project by ensuring you have selected the version called DevKit2 if you have a version of LabVIEW FPGA that is 2015 or newer.

Regards,

[thutch79]

Spot on! That did the trick. Thank you!