LabVIEW
FPGA digital output time
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This [broken link removed] page has some benchmarking info for the FPGA when used with Real Time.
Some timing numbers I received from NI doing the same thing with the analog lines showed an average time of 38uS over 30,000,000 iterations. I would thinkg the DIO lines would be similar.
Ed
Using the Abort button to stop your VI is like using a tree to stop your car. It works, but there may be consequences.
Ed,
This document and your application include LabVIEW Real-Time as part of the loop to update the output. Based on the original question I think he can close the loop on the FPGA and achieve a much faster response rate.
Closing the loop on the FPGA using the analog inputs and outputs you can achieve a delay around 5us, which is mostly due to the speed of the analog input. For digital inputs and outputs this delay will be much smaller and on the order of 10s of ns, depending on the exact implementation.
Christian L
NI Consulting Services
This document and your application include LabVIEW Real-Time as part of the loop to update the output. Based on the original question I think he can close the loop on the FPGA and achieve a much faster response rate.
Closing the loop on the FPGA using the analog inputs and outputs you can achieve a delay around 5us, which is mostly due to the speed of the analog input. For digital inputs and outputs this delay will be much smaller and on the order of 10s of ns, depending on the exact implementation.
Christian L
NI Consulting Services
The delay between reading an edge on the input line and updating an ouput line will depend on the exact requirements of your application and the implementation of the code based on that. There are two main ways to implement this type of application.
You can continuously read the input line and then in your LabVIEW code check for a change of state and if one is detected, update the output line. The delay between reading the input and updating the output will be 2 or 3 clock cycles of the FPGA (50-75 ns at 40 MHz). However since this code would be running in a loop, the loop overhead is added to the possible delay as the change on the input line may occur at any time. So the maximum delay may be around 6 to 8 clock cycles.
The second method to implement t
his code is to use the Wait for Edge function in LabVIEW FPGA. This function will wait for an edge on a digital input line and continue when an edge is detected. The delay will be 2 to 3 clock cycles, however the application will not be cycling through the loop if no edge is detected.
Depending on the complexities of your diagram you may be able to compile your code for an 80 MHz FPGA clock rate in which case the delays would be cut in half.
Christian L
NI Consulting Services
You can continuously read the input line and then in your LabVIEW code check for a change of state and if one is detected, update the output line. The delay between reading the input and updating the output will be 2 or 3 clock cycles of the FPGA (50-75 ns at 40 MHz). However since this code would be running in a loop, the loop overhead is added to the possible delay as the change on the input line may occur at any time. So the maximum delay may be around 6 to 8 clock cycles.
The second method to implement t
his code is to use the Wait for Edge function in LabVIEW FPGA. This function will wait for an edge on a digital input line and continue when an edge is detected. The delay will be 2 to 3 clock cycles, however the application will not be cycling through the loop if no edge is detected.
Depending on the complexities of your diagram you may be able to compile your code for an 80 MHz FPGA clock rate in which case the delays would be cut in half.
Christian L
NI Consulting Services
I know you can toggle a digital output (without receiving any inputs) at 40MHz in a single cycle loop, because I am doing it. It would be interesting to see what happens if you try to put both a digital read and write in a single cycle loop. Probably you would get a compiler error (?)
