FPGA - integer division I64

[ico82]

Hello All,

I just need suggestion. I have developed an FPGA tool with some discrete mathematics.

Formerly i have used the quotient & reminder block in order to divide two I64 integer types however during the compilation this function cannot be synthesized so I decided to write the code of the integer division (timing is not a constraint).

In the attached image there is my code, it works pretty well but I would like to know if exists a better way to do it, maybe some advanced block or a better code.

Thanks in advance

[wiebe@CARYA · Accepted solution]

I'd try to avoid the loops.

I'd try do make this work in parallel. The simple approach would be to simply get the 64 Booleans and do the math. But you can probably do this a little bit smarter by splitting into 2 U32s, splitting them into 2 U16s, splitting them into 2 U8s, splitting them into 8 Booleans, add the results. That might actually work in a single cycled timed loop.

Of course the lazy (and maybe best) way is to simply convert them to fixed point integers and divide them. However, I think you need to sacrifice 1 bit, or the result won't be rounded correctly: