FPGA module FIFO arbitration in single-cycle timed loop

[DarthBrader]

Hi,

I am getting error 61056, "component (one of my FIFOs) has invalid arbitration for single-cycle timed loops." All of my FIFO accessors are in single-cycle timed loops (SCTL), and all of them have the arbitration set to "optimize for single." (I have tried setting them to "none" and "normal," but the error persists). Removing certain SCTLs (or the FIFO accessors) is the only way I can avoid the error.

It is quite possible that I am trying to do too much in a single cycle with some of the SCTLs, and I may need to pipeline, but I don't think that's causing this error. I also have multiple identical accessors (the same FIFO being read in different places, or written in different places), but there should not be the possibility for race conditions or contention. I'm fairly confident that I've avoided these conflicts with case and sequence structures.

On a somewhat related note, I noticed what seems to be an undocumented limitation when using digital IO accessors within SCTLs. It appears that if multiple digital IO accessors to the same resource are used, then either they must all be inside SCTLs or they must all be outside SCTLs. You cannot, for example, write to a digital data node for conn0/dio0 in a SCTL and then later write to another digital data node for conn0/dio0 outside of a SCTL. If both nodes are inside separate SCTLs, however, everything seems to work just fine.

Is this behavior expected?
Are there similar limitations for FIFOs to those I've noticed for DIOs?
Is there something obvious that I'm missing?
Does reading or writing a FIFO take almost a full tick?
How does the time it takes to access a FIFO depend on the storage type used?
Does the use of FIFOs limit the possibility for increasing the FPGA clock speed?

Thanks for reading; any pointers would be appreciated.
~derek

[Ricardo_SR]

Hello,

I have some quick questions? How many accessors are inside a SCTL? You should only have one per SCTL and the arbitration should be set to none or optimize for single accessor.
Now it is recommended that for memory access you use shift registers and does shift registers should be initialized.
Hope this helps.
Check the following Link for more information.

Thank you
Ricardo

[DarthBrader]

Hi,

Thanks for the response.

I never placed more than one FIFO node into the same SCTL, but I do have multiple SCTLs that execute sequentially (never in parallel). Some of these SCTLs contain a FIFO node, and some of these nodes are identical (eg. two nodes that write to the same FIFO).

After some thought, I've decided this is not permitted. The docs for the FIFO node say that you MUST select arbitration = optimize for single if the node is in a SCTL. I assumed that "optimize for single" in this context meant "optimize for SCTL," but as you mentioned it probably means "optimize for single accessor." If this must be the arbitration setting for a FIFO in a SCTL, then no more than the one accessor can be used (without unexpected consequences).

I experienced some of these unexpected consequences. I did manage to get my code to compile after removing some of the SCTLs, but I still had more than one identical FIFO accessor set to "optimize for single." The behavior I observed was that some FIFO accesses would seem to succeed, but would not actually write anything into the FIFO (or would read bogus data without actually removing an element from the FIFO). I've gotten it to work by working the FIFO accessors out of the SCTLs and setting their arbitration to normal.

Why wouldn't arbitration = none be acceptable for FIFOs in a SCTL as it is with the digital IO lines?

In any case, I think I'm going to try to get everything functionally correct before trying to tighten the timing. I have some reservations about that approach, but I figure if I'm not too careless it could work pretty well.

Thanks for the help,
~derek