FPGA: multi element access on target

[Intaris]

What does the following text actually mean in regard to supported properties on my FPGA device (PXIe-7965R)?

DMA:
      Number of DMA Channels: 16
      Multi-Element Access on Target: Supported
      Peer-to-Peer Streaming: Supported

Specifically, what does "Multi-Element Access on Target" mean?

[Dragis]

On certain targets, you can configure the FPGA side of a DMA channel to allow multiple elements (data values) to be read or written at the same time (in the same clock cycle). This is achieved by allowing you to read or write an array of elements. You can configure this option from the DMA FIFO property page in the project.

[RedAG]

Sorry to butt in Intaris, Dragis, is it like "Parallel" read/write?

[Intaris]

@Dragis,

is there any documentation on this feature anywhere?  Like which version of LV supports this?

[Intaris]

Ah I see the option now on LV2012 SP1.

With a U16 FIFO we can send up to 4 simultansously, with a U32 we can send 2 and with U64, only one.

Is this 64-bit limit in hardware or may it be possible to send multiple 64-bit numbers simultaneously in the future?  We already multiplex our data into large bit numbers in order to boost throughput so this is unfortunately not very usefult o us as is.....

Shane

[Dragis]

The limits were due to implementation time. It would be possible to support larger array sizes in the future.

[Intaris]

Cool.  Kudos for U then...

[Dragis]

We already multiplex our data into large bit numbers in order to boost throughput

If you use the array functionality instead of doing the packing yourself you might actually get better performance since you won't need to do an unpack on the host side (the driver can do it in-place in memory). Might be something to try.

[Intaris]

Yeah, if we can send Booleans, U8s U16s, 9-bit FXPs and so on in an array and have thema utomagically re-converted, that would work......

We generally multiplex our "varied" parameters whereas the "samey" ones just get packed into nice byte boundaries.  I doubt there'd be a significant difference in performance (since the unpacking is trivial), but at the same clock speed for FPGA, we could increase throughput by writing more than one per clock cycle.  That's what gets me interested fast.

Shane