FPGA not enough BRAM?

[Intaris]

I'm not familiar with the workings of FFT on FPGA but here's a small tip:

You can right-click the DMA nodes and change the interface from "Timeout" to "Input Valid" and remove the case structure around the node.  Cleans up the code a little.  At the moment you have manually implemented the handshaking protocol, but the DMA node actually supports that, default is timeout-based.

https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/fpga_interface_options/

Shane

[MDemerse]

Just in case you wanted a little more info on this, here's a link to an MIT article dealing with FFT/FPGAs that might give a little more insight.  Hope it helps. 

[UMASO]

hi ngb222, 

Which version of LabVIEW are you using?  I have recently found that LV 2019 (Vivado 2017.2) consumes much larger amount of Block RAM than LV 2017 (Vivado 2015.4).  I reported the issue in the below link.   

https://forums.ni.com/t5/LabVIEW/Large-Increase-in-BRAM-Usage-for-same-WDP-FFT-settings-from/td-p/39...

If you do not have to handle multiple samples per cycle, Xilinx LogiCore IP is the most reasonable method to achieve the longest FFT on LV FPGA, as mentioned by Terry_ALE.  

[UMASO]

Hi ngb222, 

Please let me update about the BRAM usage of LabVIEW FFT IP.  Today, I received update from NI support about unexpected extra amount of BRAM usage for the IP on LabVIEW 2019.  It will be fixed on LabVIEW 2020.  

So, if you are using LabVIEW 2019, try compiling the FPGA code on LabVIEW 2018 and use that bitfile on LabVIEW 2019.  If you can wait until LabVIEW 2020 release, please just upgrade.