FPGA size calculation for cRIO

[mfitzsimons]

A customer wants to know do they need the 3M Gate FPGA Chassis for cRIO instead of the 1 M Gate.  The 4x difference in cost is getting their attention.  I found this on NI’s site:

Not all applications require the 3M gate FPGA. Unfortunately, it is difficult to determine whether an application or program will require a 1M or 3M gate FPGA. The following can be used as a general guideline when deciding whether to use a 1M or 3M gate FPGA for your application.

Is there a way to accurately determine the size of FPGA needed? 

This is our requirements for the cRIO system. 

4 Digital Inputs
20 Digital Outs (PWMs)
24 Analog Inputs
3 quadrature encoders (Using 9411 card)

[Wiebe@CARYA]

There is no way to tell upfront, besides experience.

Even benchmarking is hard; if one loop takes 70%, good change you can still copy the loop 4 times. When the compiler things it will need a lot of memory, it will compile beter to make it fit.

The loops you are describing seem fairly simple. My guess is it will fit with change left. Perhaps if you get enough fpga users to share their opinion, you can take an educated gamble.

Regards,

Wiebe.

[mfitzsimons]

Thanks!  Seems to be the common answer.

[Christian_L]

If you already have LV FPGA installed on your system you can develop the necessary VI and compile it for either target (without the hardware present) to see if the VI will fit on the FPGA. In the LabVIEW Project you can configure any of the RT and FPGA targets without needing the hardware.