FPGA timing violation on sbRIO9638 Labview 2022 q3

[Larsstumpp]

The problem is not related to anything about the loops. The problem is exclusively related to the I/O nodes. So only a data node and an indicator already trigger that error (see attached pics)

[Xonmyth]

It is tempting to think so, yes. Although, your conclusion lacks understanding of how FPGA code is compiled.

In simple terms, when you add your IO in the code, it then actually does something that is dynamic in nature. With constants, your rest of the code also become constant, at least the SCTL part. It is just a fixed logic placed on FPGA that does nothing besides stopping when the condition is met.

wsimpson0050's explanation and my finding point towards the "non-diagram component" the timing error pop-up is screaming at. 

To reach the root cause of your problem, I compiled your originally provided code after fixing the coercion dots while keeping everything else the same and that worked. I had IO nodes in there and I have sbRIO-9638. 

Don't chase a shadow. Fix coercion dots and implement what wsimpson0050 has suggested. Did you try any of the suggestions?

About your question on the IO configuration AFAIK, besides settings IO for input and output, you can set whether the IO is used on RT side or FPGA side. But this will not stop you from compiling the code. The code will compile as usual but IOs just will not update if the setting is incorrect for some reason. 

You can use this code below to do it programmatically instead of doing it from NI MAX.