FPGA timing violation

[paul o]

Hi.  I have been getting a timing violation when I compile a certain VI.  The main VI is comprised of 3 sub VIs, each in its own frame of a flat sequence.  The sub VIs each read and write to memory located on the FPGA, so there are no wires going from frame to frame.  The strange thing about this is that each sub VI compiles on its own fine, with the slowest one having a theoretical maximum frequency of 45MHz.  However, when I compile the main VI, the maximum frequency is 29MHz.  I have traced the problem code to a small VI within one of the sub VIs: when this small bit is disabled, the full system compiles fine.  When I compile the sub VI with the bit enabled, the sub VI's maximum frequency is 75 MHz.  But when I compile the full system with the small bit enabled, it gives the timing violation of 29MHz.  I have tried pipelining, sequencing, using SCTL's wherever possible inside the problem code, but nothing works.  Is there something with the flat sequence that could cause this problem that I am not aware of?
Thanks,

~Paul

[Eli_S]

Hi Paul o,

Timing violations usually occur when you have code inside a single-cycle timed loop, which requires more that one clock cycle to execute. I would imagine that the VI you mentioned is creating this situation.

Perhaps if you provide me with more information about the code and what it does, we could narrow it down further.

[paul o]

It did end up being a SCTL that caused the problem.  The loop was just in a part of the code I didn't expect, so it was very tough to debug.  I had to use some feedback nodes to pipeline a loop, and that fixed it.  Thanks!