FPGA

[sri94]

Hey! I am new to LabVIEW and had a very basic doubt.

Why isn't the divide function usable in LabVIEW FPGA, while multiplication is?
Multiplication is repeated addition and Division is repeated subtraction!

[GerdW]

Hi sri,

why do you think "divide" isn't "usable" on FPGA?

It's available and you can use it!

(It's recommended to avoid divide operations on FPGA because divide can take up a lot of FPGA resources.)

[sri94]

I asked so because while compiling, it showed me an error with the divide function, claiming not to be usable. I am using cRIO 9022 and LabVIEW 2015. Does that have anything to do with the issue?

[GerdW]

Hi sri,

please provide more details: show your VI.

(I prefer a snippet as I don't have LV2015 available right now.)

[crossrulz]

It is supposed to be that a SGL is the only floating point that is allowed in FPGA.  You probably have a DBL connected up to your Divide.

[Intaris]

It's also not usable in a single cycled timed loop.

You need to use a CORDIC divide in that case which will have quite a latency I'm afraid.

[natasftw]

Keep in mind, "repeating addition" and "subtraction" only really apply if you're discussing using multiple cycles with the add/subtract opcodes to perform the task.  If you're not, you're using another optimization.  On FPGA, optimizations require fabric.  It's generally poor form to do this.

As others have stated, you haven't given us nearly enough to help you figure out the issue.  Without code, or even the compile error, we're just guessing.  Did you include the divide in a SCTL?  If so, it's a bit strange to assume a computationally demanding function can operate within a single cycle.  What data types are you using?  You'll want FXP or SGL.  What are you dividing by?  If it's a power of 2, you'd be better off shifting the bits (in any language or target for that matter).