FPGA

[Sachin_Madhu]

Hi All,

I am trying to execute single pulse generation at very high frequency using NI 9401 on 9039 chasis. I am using Single timed loop and just passing a boolen on or off to the I/O in the STL based on calculated tick counts as shown in the attached screenshot. I want a pulse at 2 to 10 MHz range. I am using 80 MHz derived clock for this. When I try 2 MHz, for 50% duty ratio, I am getting 290 ns for the on-state instead of 250 MHz. Can someone please tell what could be the reason? I was thinking that 80 MHz clock should be able to generate 2 MHz pulse with very high accuracy. This extra 40 ns happens irrespective of the clock frequency I use. Also the ticks t1 and t2 are coming exactly as 20. Please take a look and let me know if I am missing something.

[RavensFan]

Why don't you set up your loops so all the needed calculations are done before you enter any loop?

Right now you do many calculations, the first frame ends.  You do another calculation and you loop there.  The second frame ends.  Then you have to another calculation, only then do you begin your second loop.

Try doing both sets of calculations before start either loop.  You may also want to look into the timed sequence structure.

[Sachin_Madhu]

Hi Ravensfan,

Thanks for your suggestion. I tried shifting all the calculations to before the loops start executing. This reduced the total half cycle time to 260 ns from 290 ns. So this helped. But I was wondering why it can't give exactly 250 ns? Is it due to additional clock cycle (12.5 ns) needed to move from sequence to next sequence for off state in my block (screenshot of modified code attached)?

Also if I use a 'for loop' to repeat the pulse, it adds another 20 ns. Is there a better way to do this? These small ns errors affect the frequency when I increase it to 10 MHz even though its very close at 2 MHz now.

I tried checking out the timed sequence structure, but it shows minimum clock of 1 kHz.

[crossrulz · Accepted solution]

Use just 1 SCTL.  The math can all be done ahead of time.  So you stop the loop when the total of the number of cycles is met, but you are only high up to the first limit.

Note: I was too lazy to open up an FPGA project.  I'm just using the While loop to show the logic.