回复： FPGA Memory DRAM

[jamse]

Memory DRAM  ,  I use PCIe 7821R hardware.

• Can this memory read data at intervals?

• I actually tested it, and the interval read was unstable.

  • Is it because Memory can't read at intervals?

  • I mean that my Memory DRAM reads the data from the first address to the last address one by one, and now I want to read the data from address 1, read the data from address 4 next time, and read the data from address 7 next time, each time with an interval of 3.

    I read them sequentially and the output data was normal.

    If I read it at intervals, the output gets messy. 

[jamse]

State machine read by address interval

[GerdW]

Hi jamse,

please keep things in one place instead of starting new threads for the very same problem!