Faster SPI transfer

[TurboCostas]

Hi,

I'm using the NI SPI IP (https://forums.ni.com/t5/Examples-and-IP-for-Software/SPI-IP/ta-p/3491325?profile.language=en) to transfer data from my host vi to my fpga vi. The host vi generates a 64-bit packet that contains all the control, address and data bits that are passed to the FPGA. The NI SPI IP inside the FPGA takes care of sending this packet over an SPI bus to an ASIC I have designed in the lab. The attached code works in real-time in the lab, but it is very slow when I try to send data from a large file.

In the host front panel, the enum "test scenario" chooses between 3 available scenarios:

1) sending a single packet to a single ASIC address ("Single Address"),

2) initializing the ASIC address by writing the IQ data on the front panel sequentially to all address locations of the ASIC ("Initialize"), 

3) and sending data from a file to the ASIC memory; the first row in the csv file is written to the first address inside the ASIC.

My problem is that my approach is very slow when I initialize or write from a file; There are 8192 addresses to write to and it takes about 10 minutes to fill up the SRAM. The SPI clock is at 4MHz in the lab and I verified that the data was correctly written to the ASIC memory by reading back via the SPI. I believe the bottleneck is that the host vi waits to receive a "ready for input" acknowledgement from the SPI vi inside the FPGA code, which slows down the data transfer.

I tried putting most of the code inside the FPGA and passing the entire array (8192 x 1 of U32) read from the file via a front panel control, but I got an error during FPGA compilation that the amount of bytes exceeds what the control can support.

Is there a faster way of transferring such a large array to my FPGA? I looked into DMA FIFO (my USB 7845R supports 3 DMA channels), but didn't manage to make it work. In a nutshell, I passed each 64-bit packet via a DMA FIFO from the host to the FPGA and had the "ready for input" signal checked locally by the FPGA code. However, the FIFO timed out and nothing was passed to the SPI vi.

What is your advice on speeding things up ?

[wiebe@CARYA]

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@TurboCostas wrote:

I believe the bottleneck is that the host vi waits to receive a "ready for input" acknowledgement from the SPI vi inside the FPGA code, which slows down the data transfer.

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If that is the bottleneck, why would a faster transfer to the FPGA speed up things?

It could be the hardware (presumably giving the "ready for input") is the limit?

[TurboCostas]

I moved the code that checks for the “ready for input” signal inside the FPGA code, but the speed didn’t improve. So, I assume that the slow execution speed is still due to the communication between the host and FPGA vi...