Flex RIO 7966 R and IO Module 6581: Clip Details

[chinnasoliton]

Hi All,

   I am using Flex RIO 7966 R and IO Module 6581.

In the VHDL files given by NI, there are 66 X 2 GPIO inout pins available as adapter module IO and 23 X 2 (Connector A & B) write and read pins which are exposed to LabVIEW FPGA.

 Even though those 66 X 2 GPIO pins are of type inout, they are used either as input alone or as output in NI 6581 base file.

Refer the following code in NI 6581 base file,

aDdcaDataRd(7 downto 0) <= aUserGpio_n(19) & aUserGpio(19)
                                               & aUserGpio_n(18) & aUserGpio(18)
                                                & aUserGpio_n(17) & aUserGpio(17)
                                                & aUserGpio_n(16) & aUserGpio(16);
aUserGpio(0)      <= aDdcaDataWr(0) when rIoModGpioEn='1' else 'Z';
aUserGpio_n(0)  <= aDdcaDataWr(1) when rIoModGpioEn='1' else 'Z';
aUserGpio(1)      <= aDdcaDataWr(2) when rIoModGpioEn='1' else 'Z';
aUserGpio_n(1)  <= aDdcaDataWr(3) when rIoModGpioEn='1' else 'Z';
aUserGpio(2)      <= aDdcaDataWr(4) when rIoModGpioEn='1' else 'Z';
aUserGpio_n(2)  <= aDdcaDataWr(5) when rIoModGpioEn='1' else 'Z';
aUserGpio(3)      <= aDdcaDataWr(6) when rIoModGpioEn='1' else 'Z';
aUserGpio_n(3)  <= aDdcaDataWr(7) when rIoModGpioEn='1' else 'Z';

aUserGpio(4)      <= (not aDdcaDataWe(0) ) when rIoModGpioEn='1' else 'Z';

Here the GPIO(0) is used only as an output and GPIO(16) is only used as an input.

In spite of being declared as inout port. Also the direction control/ Write enable pin from LabVIEW FPGA port is not at all used in the clip but directly linked to one of the GPIO port.

Is there any specific reason for it?,

Is LabVIEW is taking care of direction control while compilation?

If we wanted to use those GPIO pins as both inputs and outputs, can we use it?

If so what are the considerations for that? 

I have attached the NI generated clip files for reference.

Please help me with the above questions.

Thanks in advance,

Regards,

Chinna Thambi M

[Terry_ALE]

Typically the FlexRIO Adapter Module CLIP isn't modified.

[chinnasoliton]

Hi Terry,

Yes the attached file is not the modified clip file.

Just to show that the GPIO pins are being used as either inputs or as outputs, I have attached it.

Just wondering whether we can edit that to use one of the GPIO pins which is used as input to an output and viceversa.

Thanks for the response.

[David-A]

The 6581 has a series of digital line buffers on it that seperate the FPGA from the front panel of the module. If you look at the 6581 getting started guide it provides a figure of this on page 10.

The digital input/output buffers that seperate the fpga from the front panel of the module also perform line level translation to the reference voltage so that the signal sees the desired single ended voltage regardless of what the fpga IO is operating at. The reason that a GPIO is set to read only or write only is because it is connected to a read only or write only buffer. GPIO 16 is connected to a read buffer. GPIO 0 is write only because it sets the selection circuitry that puts a write buffer into high impedance mode if the line is intended to be reading from the front panel of the module instead of writing to it.

So the question isn't "can you make a specific GPIO line inout". The question is "should you make a GPIO line inout". The answer is probably "no you shouldn't".