GENERATE SPI

[kenoss]

. 

New to me, the project requires that an SPI protocol signal generating system be developed for communication.

The end product will be a Master control/monitoring system (LabVIEW platform) that will produce SPI signals whose characteristics are variable.  The variable parameters include:

• Length of transmitted WORDS in binary bits
• Serial clock frequency
• Clock polarity and phase configuration

The core function of the software will focus on “Bit-bashing” to produce signals.  Advise on this is very welcome.

Initial background research has located the following NI sources as relevant to the project:

http://zone.ni.com/devzone/cda/epd/p/id/6263 

http://zone.ni.com/devzone/cda/epd/p/id/6265 

https://forums.ni.com/t5/Example-Code/Implementing-SPI-Communication-Protocol-in-LabVIEW-FPGA/ta-p/3... The VI example herein appears particularly close to project requirement

I have a cDAQ-9172 chasis with a NI 9401 high speed DIO module that I intend to use for development. 

It is the software writing that I most concerned about.  Any advise on simple development of this system will be greatly appreciated.

Many thanks

Kenoss

[Mark_SAI]

Hi,

If you generate SPI signals with a cDAQ, the maximum clock rate you will acheive is only 500 hz due to the fact that you can only implement software timing. This leads to further complications in that windows cannot ensure deterministic timing so the clock rate could vary. Typical SPI clocks in typical applications would be around 500khz-10Mhz. You would fare much better with a compactRIO which will happily use that code in the 3rd link you posted in its onboard FPGA, allowing a clock rate of 10Mhz or possibly more.

If you are looking for a lower cost solution than a cRIO, then a USB-8451 may be suitable, depending on your requirements.

[Ben]

Cheetah SPI host adapter and LabVIEW drivers are provided.

Plugs into a USB port, each unit support up to 3 slaves.

Ben