GPIO Flickering

[ohmsean]

Hi,

I'm working with a sbRIO 9641 system, and I'm getting some very odd flickering from my digital I/O pins. I'm trying to send data from a microcontroller to the FPGA, but some of the I/o lines flicker on even when I'm holding them low.  Any idea how I can solve this problem?

[Burt_S]

Hello,

This is interesting.  What do you mean by flickering exactly?  Do you mean a quick pulse?  If so, is it random or periodic and how fast of a pulse is it?  Also you mentioned that you are trying to send data from a microcontroller to the FPGA.  If so, then the microcontroller must be driving the line and is likely reponsible for this behavior somehow.  One possible workaround would be to implement some form of debounce filtering in the FPGA so that it essentially ignores the 'flicker'.  Hope this helps!

[ohmsean]

I do not think it is the MC because when viewing the lines with an Oscillscope I notice no noise that could cause the flickering.  Additionally, it appears to work correctly when there is just one loop reading in the inputs, but when I add another parallel loop outputing a very fast clock (~6 MHZ) on PORT0/DIO4 the flickering appears.  Could internal noise generated by that fast clock be causing interference on the lines?

Message Edited by ohmsean on 04-08-2009 06:22 PM

[iled09]

[different member working on ohmsean project]

Actually, I do notice some noise on the MC driving the line.  When the lines are connected and the FPGA is not running, there is minimal noise.  It is only when the FPGA is also running that the noise appears on the line.  Would applying some sort of low pass filter to remove the noise help?  How can I do this in labview FPGA?

[ohmsean]

I think I've narrowed the problem down and it is not the MC.  I have two loops running in parallel: one input loop reads in the state of the inputs constantly while another timed loop outputs a very fast clock signal.  The input loop is set up to detect positive and negative edges on one of the lines.  It works fine when I turn the clock output off, but when I turn the clock output on, the Input line now rapidly detects positive and negative edges.  It seems like the clock output is causing significant crosstalk on the the input line internally to the sbrRIO.  Any idea how I can fix this?

[Burt_S]

Hmm, that is interesting.  There are a couple of things I would do to fix this problem.  The first would be to try and separate these channels as much as possible.  I would try insulating them from each other and putting them in DIO ports that are not adjacent. 

The other thing I would do would be to implement some form of debounce filtering on the FPGA.  Essentially, if you know the highest frequency signal you would expect on a port, you can poll the DI and only accept it as an input if it constant for a certain amount of time (a time less than your shortest valid signal period).  As long as these noise spikes aren't constantly happening, you will be able to ignore them.  I hope this helps!