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Gated semiperiod counting DaqMY LV7.0 + NI6602

I am converting an application form traditional DAQ to DaqMX and am having trouble with the new conventions.
The application uses a common gate to count gated events on multiple counters (5 total counters employed). An event causes 5 pulses of 500us 0.5 duty cycle and the counters must share this gate source and count TTL pulses coming from 4 different photon counting PMT. Essentially I am measuring a optical decay curve (10 points of each 500 microseconds)when each event occurs. This was easily accomplished using traditional DAQ but I cant get it to work under DaqMX (version 7.2). My solution for this scheme under traditional DAQ was to set up 5 tasks, Task 1-4 used counters 0-3 on the 6602 set for semiperiod buffered counting from the source terminal of each counter and the gate was configured to share a common PFI line counter 5 also shared the common gate but used the internal 80MHz clock as a source (This was so I could have a time stamp of each event since the freqency of everns is not a constant. When setting up a semiperiod under DaqMX I can not get the source to change from the internal clock to the PFI corresponding to a counters "source" pin. Any help would be greatly appreciated.

-Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Hello Paul. Thank you for contacting National Instruments. DAQmx makes it easy to do what you described. There is an example program (Meas Buffered Semi-Period-Finite.vi), that if tweaked a little, will do what you want. Add a DAQmx Channel property node between Create Channel and Timing. Select Counter Input>>Semi-Period>>Input Terminal. The input terminal is the source of what you are measuring. Next, change the Timing to Sample Clock. The source of the timing is the gate. This is how you change the source and the gate.

When I first did this I only had Onboard Clock as an option. I went into MAX and Reset Driver for Traditional NI-DAQ. After I did this, the whole list populated. I hope this helps! Have a great day!

Marni S.
National Instruments
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I tried what you suggested but am still getting errors, when I start the task, the semi-period will not let me use the sample clock as a timming option, only implicit or on-demand. I will keep at it I am sure something will work since I had it running fine with traditional DAQ and the same hardware.

-paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Implicit timing means that if you don't have a hardware connection to the source of the counter, it uses the onboard clock. However, if you do have something connected, it uses that. If you want to connect the source to a PFI line in software you could use implicit timing and change the source for the Sample Clock. To do that add a DAQmx Timing property node and select Sample Clock>>Source. Give this a try. Please let me know if you have any questions.

Marni S.
National Instruments
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Thanks for the help, I was able to get my application to work perfectly, I created a semi-period counting channel then set the timing to implicit continious timing and modified the following channel properities:
1. CI.Dup.CountPrevention = True (I need to allow for zero counts to be valid)
2. CI.SemiPeriod.Term = gate pfi (this allows me to gate multiple channels on a single pfi line)
3. CI.CtrTimeBaseSrc = Source (Pfi line wiered to my PMT ttl line, this is what I need to count)
4. CI.CtrTimebaseRate = 200000 (Maximum expected rate of TTL source pulses, is actually usually much slower ~1-1000kHz)
5. CI.CtrTimeBaseActiveEdge = rising (probably not needed)
6. CI.DataXferMech to DMA (since the 6602only has 3 DMA channels and I configured 4 channels in this mannor, I had to set the last channel to Interrupt, but the application has no trouble keeping pace with the data.

After configuring the channel I start each channel then read them in a loop, now everything is working great, thanks for pointing me in the reight dirrection

-Paul
Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
0 Kudos
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