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HP 8753D Operation complete status bit.

The HP 8753D network analyzer sets the zero bit of the status register to a one when it completes some of the more involved operations. Can anybody explain to me how to detect this so that I can keep my vi and the analyzer in sync?

Thank you

TeBlues

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Thanks for the pointer

T.B

 

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I remember taking a look at those drivers a while ago since I was looking to have a VI to do a 2-port or1-port cal . Didn't find it in that list, nor was there anything in there that dealt with the status registers. The 8753D uses what I refer to as "old-style" commanding, i.e., non-SCPI. To use the status register bit method you need to keep reading the event status register (ESE?) after performing your operation until that bit is set to 1. Essentially this is a polling method.

An alternative method is to use the OPC? command. In the manual referenced in the previous post there is a list of commands that are OPC compatible. This means that you first send the OPC? command, then you send the command you want the network analyzer to perform, and then you follow up with a VISA Read. The VISA Read will return once the operation is complete on the network analyzer. The return value of the VISA Read should be "1", indicating operation complete. This is nice in the sense that you don't need to use a polling mechanism to keep checking the event status register. However, a caveat is that you will need to increase the VISA Timeout to prevent the VISA Read from timing out if the operation takes too long. In the drivers I have this is the method I employ.
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Hello,
The following post addresses this same question.
 
Regards,
Angela
Applications Engineer
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