Happily merging two cRIO Real Time VIs: Analog Input and Digital Output

[JeffKrol]

Howdy,

I need some assistance with some cRIO code.  The goal for the code is to be able to acquire an analog input from the NI 9234 c series module and be able to send a digital "pulse signal" (first low for some time, t1, then high for some time, t2) out from an NI9401.  Separately, I have written code to perform the two tasks.  However, when I add the RT digital output pulse code to the RT analog input pulse code, the DMA FIFO overflows due to the way that my digital pulse output code works.  Currently, there are two reasons that the FIFO overflows:

1. The digital output code is waiting in a while loop (waiting for "Send Pulse" to become true), preventing the AI loop from emptying the FIFO buffer
2. The FIFO is not emptied fast enough, depending on how long the pulse periods (t1 and t2) are.  The way I am keeping the pin high or low for a set amount of time is by issuing a sleep command, which blocks the AI loop from emptying the FIFO.  (Is there a "better" way to sleep?)

I have attached images of my FPGA and RT codes.  Please give me a suggestion on how to marry my two RT loops for happy resource utilization!  Thanks.

[A_Patel]

Hi Jeff,

You can increase the size of the FIFO. Have you tried this?

Flash

[JeffKrol]

I have thought about increasing the size of the FIFO.  In addition, I was also planning on making the low pulse length very short (since that doesn't matter too much for my application).

While your suggestion might be a temporary solution for me, if I were to want to output a continuous digital signal (as opposed to just one low-high-low burst) on that line, what could do I do with my RT code to prepare for that scenario?

Thanks.

[A_Patel]

Hi Jeff,

Why don't you use two loops and wait for the the FIFO to have an element to read it?

Here is an example of using DMA FIFOs.

http://zone.ni.com/devzone/cda/epd/p/id/2649

Flash

[JeffKrol · Accepted solution]

I figured out a quick way to solve this problem.  I moved the timing of the digital pulse onto the FPGA.  So whenever I issue a boolean, the FPGA generates a waveform with the parameters I set (a pulse in my case).  This works because the FPGA loops run in parallel, I believe.  Therefore, when I issue a wait command in the FPGA digital output loop, it doesn't prevent the analog input FPGA loop from running.  I have attached a picture of the code.