High Speed Data Acquisition from FPGA using DMA FIFO

[ecksor]

There is a tutorial for data acquisition here:

http://zone.ni.com/devzone/cda/tut/p/id/4534

but because it has a for loop iterating 4 times, I think the speed of data transfer will be 10MHz instead of 40Mhz.

I am thinking of higher speed acquisition, up to 40 MHz.

Any ideas?

Beside this, I have a quastion about difference of using While Loop or Single-Cycle Timed Loop as a main structure on FPGA. As far as I understand the Timed Loop is supposed to be most precise loop in such high speeds. So for these applications is not better to use Timed Loops?

[Dragis]

The tutorial you mentioned is a very simple example just used as a Hello World application for DMA channels with the FPGA module. One thing to keep in mind when writing code for the FPGA is that there is the operating speed of the device and the actual operation timing of the constructs on the diagram. Like you said, the example does not use the Single-Cycle Timed Loop (SCTL) but is instead throttled by the Loop Timer. The Loop Timer ensures the I/O is sampled at the appropriate times and the For Loop plus DMA FIFO Write node shuffles the data to the host. The timing of the samples is ensured by the Loop Timer, the actual code is running at what ever clock rate the diagram is configured for (the default is 40 MHz).

To your app, if you actually want to acquire data at 40 MHz, you'll probably need to use the SCTL. You will also most likely have to compress the data into larger chunks so you can transfer multiple values to the host at one time. On the other hand, if you don't need to sample the I/O at 40 MHz but just want to transfer the data at that speed, you might be able to use the standard For Loop and Loop Timer programming model.

[ecksor]

Thanks for your response.

My problem arises exactly at the point you suggested,

I am trying to acquire stream of 5 digital lines through DMA FIFO to the host using a FPGA. And I need it to be high speed up to 40MHz.

Because of limits in number of DMA, I need to interleave these 5 lines and pass them by FIFO, but FIFO doesn't accept arrays, and also not possible to put for loop in SCTL or delay it to transfer all 5 elements.

[Dragis]

In that case, you can use the Boolean Array to Number primitive to generate a single U8 value to send through DMA. On the host, use the Number to Boolean Array primitive to pull the values back out.