Host to Target DMA question

[lokomokoeh]

Hello Guys,

I have a problem regarding DMA Access from Host to Target. I access DMA at an interval of 1.7uS I get 12 U32 data from DMA every 1.7uS, problem is, I can see that DMA can take more time than the normal. Is there a more efficient way to get 12 U32 data at a time?

Thanks,

[Jeremy_B]

Hi lokomokoeh,

What hardware are you using?  Are you using LabVIEW Real-Time?  How long does it actually take, and how are you measuring the time?

[lokomokoeh]

Hello Jeremy

I am using NI 7833R FPGA module. what I did was to place read DMAs in a sequence structure (1 in each frame so that makes 12 frames). then inside each frame, I placed an output port which I set to True then false then true agan while passing through the sequence structure.

When I run the program, I can see that it takes around 125nS for each DMA access, But there are times that it takes more time to complete 1 access which takes more than 125nS.Most of the time, The 12 U32 data takes 1.5uS to complete. But due to the unknown reason, it sometimes takes more time to access DMA.

Thanks

[Jeremy_B]

Hi lokomokoeh,

Could you post your VI?  How are you measuring the time between your port toggling?  Is this a target to host DMA FIFO?  If so, how fast are you removing elements on the host side?  If this is for transferring data to your host, you might want to use a larger FIFO so the host has more time to access the buffer before old values get overwritten.