Hi All, I've programmed a 7975R FPGA to perform a cross-correlation between data read from two separate disk drives (HDD 8264/8265 raid arrays). The data sets are quite large ( >100GB ) and so the FPGA is used instead of standard processors to gain a significant advantage (>100 x) in the processing time. To perform the stream, I first fill up the host buffer for both transfers, start the DMA FIFO transfers, and then it is managed (on the host end) by two DMA FIFO transfers that are running in separate threads (while loops). The two threads are effectively identical, using the TDMS Advanced Asynchronous Read VI to perform the transfer. Now the problem is that I keep getting FIFO timeouts which I believe to be due to underflow on the FPGA end in that the host processor cannot buffer data to the FPGA through the DMA engine quick enough. I first compiled the FPGA at a rate of 125MHz, which will immediately times out. When I lowered it down to 80MHz, it will transfer successfully for some length of time but consistently will timeout (underflow) after ~ 1-2 minutes. I lowered the FPGA rate even further (down to 40MHz) and it performs roughly the same, which I found surprising. I am now trying it at 10MHz, but this is too low for our application in that it will take far too long to process the data. I am using an 8133 controller. The data is streamed with 16-bit resolution/sample. I tried changing many of the parameters (FPGA FIFO Size, Host Buffer Size, Write Region size) and there are slight differences in the results, but after a few minutes of the application running, it times out. At 40MHz the transfer rate is 40M x 2 (hard drives) x 2B (bytes per sample) = 160 MB/s, which is well within the specs of the system (~ < 800 MB/s or so). The behavior is a bit confusing as well, in that I don't gain much in the timeout rate from when I go from say 80 to 60 to 40 MHz. When I try looking in other posts, it is generally concerned with transfers from the target to host and I can't find much resources in dealing with this when going from host to target. Happy to post any code, but first it would be nice to hear thoughts on what I just described. NKM

Not sure if I get the entire picture... Underflow is usually desirable. Why not simply skip functionality if there is a timeout?

LabVIEW

Solved!

Can you share your code. I have txt file consisting of 8-bit integers I want to transfer them to FPGA target using DMA

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