Hi,
I am testing an interface card which acquires 16 bit digital data at every 5 microsecs along with Dvalid pulse. Dvalid signal is high to low edge signal each time indicating the presence of 16-bit data with OFF time 1 microsecs (variable) & ON time of 4 microsecs (variable) making total of 5 microsecond period in all the possible cases. Interface card stores this input data in temporary buffer. It has got sync circuit which has REQuest signal & Acknowledge signal to have 2 way handshaking protocol.
I am using 2 PXI-6534 modules, Ist acting as source of data, IInd acting as data reader.
In Ist PXI-6534 card, I am using Continu
ous handshake output Vi, i have connected CPULL to +5V pin to make it default high. I m fetching a signal of frequency 200KHz (5 microsec period) to REQ1 of this card. ACK1 is connected to Dvalid pin of interface card.
In IInd PXI-6534 card, I have connected REQ1 & ACK1 signals to respective singals of interface card. I am using Continuous Handshake output vi, i have connected CPULL to +5V pin to make it default high. Whenever data comes from the Ist card, interface card generates high to low REQuest signal connected to REQ1, IInd 6534 card acquires data asserting ACK1 signal after acquisition. This cycle repeats.
Now problem is that i m storing the generated & acquired data in 2 binary files & later i am comparing them. Here i observe that i am missing some data in between. What could be the reason? I have tried to set all the signals status in hardware & vi. Still i am not able to match the generated & acquired data. I am attaching both the vi.
Thanx in advance for your help
,
Best Regards,
Nirmal Sharma