How to clean FPGA to make faster compiler

[hsw9797]

i have some project that i compiled in FPGA (crio-9039)

my problem is compile is more and more slower. 

i guess FPGA code accumulated in FPGA because i can run many project with no compile process 

i initialized crio in NI max but situation is same 

how can i delete useless FPGA code compiled in FPGA target?

[Terry_ALE]

Can you expand on what you need and do not need?

[GerdW]

Hi hsw,

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@hsw9797 wrote:

i guess FPGA code accumulated in FPGA  

how can i delete useless FPGA code compiled in FPGA target?

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You don't "accumulate" code in the FPGA, you build a bitfile from your FPGA VI.

When there is "useless" code in your VI then you should delete it - or use the disable structure to comment it out...

[hsw9797]

I think i wrong understand compile.

Compile mean convert labview code to fpga programming language

And then store logic in fpga chip

So after i compiled fpga vi, i can run without no compile process because logic is stored in foga chip 

right??

but i thought if i can run several fpga vi without compile process, several logic is stored in fpga

is it wrong?? 

if it is wrong why my fpga compiler is getting slower??

Think you

[Hooovahh]

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@hsw9797 wrote:

I think i wrong understand compile.

Compile mean convert labview code to fpga programming language

And then store logic in fpga chip

So after i compiled fpga vi, i can run without no compile process because logic is stored in foga chip 

right??

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Nope.  Once your LabVIEW code is compiled to a binary for the FPGA, it is stored on your computer.  When you go to run the VI LabVIEW first sees if there is a binary already made for the VI you have.  If there is it downloads it to the FPGA, and then you can see the VI running on the FPGA.

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@hsw9797 wrote:

but i thought if i can run several fpga vi without compile process, several logic is stored in fpga

is it wrong?? 

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Yes this is wrong.  You can only have one VI's worth of code running on the FPGA at once.  Multiple binaries can exist on your computer, and running the corresponding VI will cause that binary to be downloaded to the FPGA and ran.

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@hsw9797 wrote:

if it is wrong why my fpga compiler is getting slower??

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I don't think we have enough information to answer the question for definitively.  I suspect you are adding more logic to the FPGA VIs and that is using more resources.  If you use too much resources, the FPGA needs more time trying to optimize the code to fit.  The longest compile that was successful for me was about 4 hours.  As others have said you can disable parts of your code and the compile time should be reduced.  Then once you are confident that all the pieces work independently, enable them all and compile it as one big binary.  If you change your VI at all, a full recompile will be needed.  Attaching your FPGA compile report might help in knowing why it is taking longer.  Also you never mentions what "long" is to you.  Is it taking 4 hours?  And additionally have you taken any FPGA training?  I think some of this should be covered there.