How to configure Spartan-6 I/O on sbRIO 9626

[DiracDeltaForce]

Hello,

I am currently developing a VI using the sbRIO 9626 to control various data collecting instruments. It is necessary to have the unused outputs on the sbRIO pulled down to ground in order to prevent issues with our devices. I know that it is possible, when programming a Spartan-6, to designate whether the I/O's are pulled up or pulled down. Since this same FPGA is used on the sbRIO 9626, I would suspect that there is a similar command to set the state of the RIO I/O's. Could someone give me some insight on how this would be done?

Thanks for the help.

[Wayne_T]

Hello,

I checked the operating instructions and see the I/Os are defaulted to tristate before and during configuration, and unused I/Os remain tristated.  You would need to implement pull-up/pull-down resistors to ensure a start up value.  Alternatively, you can have develop a configuration vi and download to the flash memory that has start up states.

OEM OPERATING INSTRUCTIONS AND
SPECIFICATIONS
NI sbRIO-9605/9606 and
NI sbRIO-9623/9626/9633/9636

http://www.ni.com/pdf/manuals/373378d.pdf

Downloading an FPGA VI to the Flash Memory of an FPGA Target (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgahelp/downloading_fpga_vi_to_flash/

[DiracDeltaForce]

Thanks for the response. For this project, we do not want to individually ground each of the I/O's, so the configuration file seems to be the answer. I am familiar with reading and outputing from the DIO, but I haven't been able to find any subvi that allows you to set the state of the IO port. Could you possibly point me in the right direction? I appreciate it.

-Zach

[tannerite]

Zach,

I believe Wayne is talking about creating a VI that configures the DIO, but that can only be ran after the bitfile is loaded. There is a pin on Spartan-6 that determines if the line should be tristated or not, the HSWAPEN pin. We pull this pin high so that the DIO is tristated when the FPGA is powered but a bitfile has not yet been loaded. We tristated this line so users have the ability to pull the line up or down depending on their application; therefore, it is required that the DIO lines that you need to have configured before the bitfile is loaded need to be externally pulled.

[DiracDeltaForce]

Ah ok thank you for that information. We are not terribly concerned about having the DIO tristated upon start-up and before loading the bitfile. We mainly want to know if and how we can pull up or down the DIO ports during sbRIO operation. How do we go about setting this for each DIO with a vi? 

-Zach

[tannerite]

The Spartan-6 has the ability to set either a weak pull-up or pull-down resistor, but this is not a configurable option within LabVIEW or LabVIEW FPGA. If you would like to achieve the same result, NI recommends that you add pulls external to the sbRIO.

If you would like to see this feature in future products, I would recommend adding this to the Idea Exchange.