How to manage latency in sctl on FPGA

[Rufnek]

Hi everyone,

I've design an algorithm that read values from a FIFO in order to accumulate and store them.

The first FIFO value must be added to the 168th FIFO value, the second value must be added to the 169th and etc. I'm using a memory item that can store 167 values and when I read the FIFO value, I also read the memory item.

This algorithm is well working if the latency is 0.

I'm using "High Troughput Add" node and in order to compile the VI at high frequency, I have selected the "Register outputs" option. So the latency is increased to 1 cycle. With this setting enabled, I obtain a strange behaviour : it seems that the first FIFO value is accumulated and stored at the second memory index (or something like this).

I think that this behaviour is due to the increased latency because with a latency of 0 it works well.

Please find below the algorithm.

Can anyone help me to solve this issue ? I think that I must add some z-1 node somewhere, but where ?

Many thanks for any help,

Regards,

[nathand · Accepted solution]

It would be more helpful to attach your VI than the image.

Do you need the register? Do you even need the high-throughput math functions, or is the standard LabVIEW Add sufficient?

Adding a register on the output means that the function will take an additional cycle to provide a valid value, so you need to account for that in your algorithm. That is, on one loop iteration you'll set the inputs that you want to add, and on the following iteration you will get the results of the addition.  So you should change the memory address where you store the value to take this delay into account.

[Dragis]

You are right. Since you increased the latency (the time it will take for the data to get through the adders), you need to also insert delays on the other parallel data paths. In your case, you'll need to insert a delay (feedback node) into the address line near the top of your code to keep the address in sync with the data.

You may also need one of the "scan" line as well, but I wasn't sure what it was used for and didn't show up in the path of the memory blocks so I left it out.

[Rufnek]

Thank you so much for your help !

I can't use classical add node because I've got a timing violation.

I changed my algorithm in order to use 2 address indexes : the first one is managing the read memory node and the second one is managing the write memory node. That's well working !

Regards,

PS : next time, I'll directly send my VI 😉