How to optimize the FPGA vi in 40Mhz clock?

[Bharathi]

Hi

I am using LabVIEW 7.0 and LabVIEW FPGA 1.0. I was trying to simulate the serial read/write implementation example and I am not able to successfully compile the code for read implementation at 40MHz where the data bits is 32 and baudrate 100KHz. But I am successfully able to do write implementation at the same baud rate using the 40MHz. Can somebody help me to use optimizing techniques to do this? Or is there any other way to achieve this?


Thank you
Subramania Bharathi

[Kristi_P]

It sounds like you are having a difficult time getting all of your code to fit on the FPGA. If so, there are some best practices for optimizing your FPGA code to conserve space. A big tip is to avoid using arrays. Minimize array usage by using look up tables or by accessing the onboard memory with the read/write to memory VI's. You should also minimize use of front panel objects, use appropriate datatypes, avoid using the Quotient & Remainder function, and try to use a constant (rather than a front panel control) scaling factor when calling the Scale By 2^n function.

You might also consider upgrading to LabVIEW 7.1 with FPGA 1.1 as it adds more tools that are good for efficient size and speed optimizations. The new Single Cycle Timed Loop and the new FIFO's are good examples of this. Take a look at the LabVIEW FPGA 1.1 User Manual for more information about these new features.

Another good document to look at on the NI Developer Zone is Utilization of LabVIEW FPGA Structures/Functions/Data Types on an FPGA. It provides some good general tips, but it was mainly created for LabVIEW 7.1 and later.

If you have any other question, please post a reply.

Regards,

Kristi H
National Instruments