12-11-2008 09:15 AM
PCI-7830R
LV 8.2
What I was trying to do is to use multiple DIO to generate pulse at different sequence. Mode one is to automatically sweep from DIO1 to DIO20; mode 2 is several DIOs generate pulse simoutaneously. So I use a case structure to make the selection, in the mean time, I set up two for loop in each case so that I can use multiple pulse generations. For example, in scanning mode, if I set 2 exposures, it sweeps from 1 to 20 then do it again.
Then I need to get the loop sequence number, i of each scenario. So I put an indicator within the first loop, and create a local variable of it and put in the second one. Running the FPGA vi alone, I can see the indicator change in each case from 0 to N-1, N being the for loop time.But in the host vi, I tried to add this indicator as an element in the read/write invoke method, in the debugging mode, I could only see it directly jump to N-1 without all the changes I saw in FPGA vi.
Is it possible to get this number passed correctly from FPGA vi to the host vi? Thanks
12-12-2008 08:17 AM
Mr.Nobody,
Why are you using the Local Variable again, I do not quite understand that. Additionally, when you performed this test was your FPGA VI in debug mode (viewing front panel) or did you deploy it? It is possible that it happened faster than the property node of read/write could access the indicator's updates. You might want to look into using a FIFO to ensure that you catch every data point.
12-12-2008 09:42 AM
Thanks for the reply Jared.
Excuse me if it looks incorrect, but I'm new to FPGA programming, so I would have to look into the FIFO you referred to. I used local variables because for one thing I have several different cases containing for loop in each of them, and I only want one indicator for the "i". If I put the indicator out of any for loop, it's only gonna show the last number which is N-1. For the other thing, it seems like property nodes are not allowed in FPGA vi. And by doing this, I can see the i number changing from 0 to N-1 in each case, well, in FPGA vi's front panel. But while I ran the host vi with everything, the indicator in host vi's front panel only showed the last number N-1. It may be the reason you said, it happened too fast before the indicator in host vi can catch it.
What I want to realize is to group the data I collect in host vi, for example, when I choose multiple exposure in each mode, and the FPGA runs 1 through 20 then do it again, I want the data stored in two groups using the loop sequence number as the seperator in file name. So it goes like 1-1, 2-1.......20-1; then 1-2, 2-2,.....20-2.
12-15-2008 05:13 PM
Mr.Nobody,
When you are running the Real-Time code and viewing the indicator as only N-1 and not seeing the rest, are you running the FPGA also in debug mode or are you running it without the Front Panel visible? If you slow down your FPGA VI are you able to see these updates in your Real-Time? Have you had the opportunity to run it slower yet? You should be able to do what you are wanting to do with the archictecture you are using. The main reason I suggested the FIFO is because it will ensure that you do not lose any data points. Both methods will work, but the FIFO should work at a much higher speed and much more reliable.
12-16-2008 10:51 AM
Jared, basically there're three scenarios:
1. Running the FPGA vi only, and I can see the indicator in FPGA vi showing the correct numbers changing from 0 to N-1
2. Running the host vi in standard mode, with front panel visible, I only see the numbers jumping directly to N-1
3. Running the host vi in debug mode, with the yellow bulb on, so everything slows down, and I can actually see the numbers changing from 0 to N-1, altough from the oscilliscope my pluse generation has long gone ( pulses are still generated at the normal speed/duty cycle, so they end faster than the numbers in that host vi indicator at debug mode)
It looks very likely that it's too fast for host vi indicator to catch.
12-17-2008 12:22 PM
Mr.Nobody,
Take a look at this document for information on how to use a FIFO, I think this would work best for your operation. Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices