We are using three PXI-6552 cards to generate/analyze an SRAM. One card each is used for Address(A), Data(D) and Control(C) signals. Rates approximate but indicative of the relationship of signals. We would like the A and D cards to be synchronized at a 1MHz rate but the C card would run at a 16MHz rate. This card would generate 16 Words that would repeat for each Word of the A or D cards. We have used the brute force method in the past but now need to be more efficient with our memory usage.
We don't want to repeat the C card 16 word vector say 1 million times in memory because we don't have infinite memory. We expect to use scripts so each 6552 card memory is filled once and each waveform pattern is called in the desired order. Another way to visualize this is A will always increment from 0 to 1Meg (1Megaword depth), D can be many data patterns (All Zeroes, Checkerboard, Increment, Pseudorandom, and their inverses) each 1Megaword in depth. C will be only two patterns, Write and Read, each 16 Words in depth.
When we try to run cards at different rates in the same chassis we get clocking error messages.
How would the clocking and triggering be set to do this? Can we use the backplane as much as possible or do we need to use the PFI, DDCCLKOUT and STROBE signals at the end of the 68 conductor cable to provide the synchronization and handshaking?
Does it all work out if each card uses the same 10MHz Reference Clock so the PLL would create the internal card clock? We need to have everything synchronized even at the end of the long vector patterns.
Thanks in advance.
Steve
