How to solve error -61202 with using two FPGA references

[XXC796 · Accepted solution]

They are different FPGA references, and I have solved the problem now, there is a VI called 'close FPGA reference' VI, add this VI between two different references, then it will close one reference before opening another one. So I can use different references in one program.

Thank you all the same.

[Intaris]

But what I don't understand is: You said you wanted to do both functions at the same time.  What you now describe is doing one after the other, certainly not both at the same time.

Are you sure your code is doing what you want this way?

[XXC796]

Well...what I mean exactly is to use two different FPGA references in a while loop, I am sorry for my inaccurate description.

[Intaris]

You do realise that the code doing the PWM output and the code doing the acquisition are not running at the same time, right?  If that's expected and OK, then I'm happy you've solved your problem.

[XXC796]

I am not sure if I can use two different FPGA references in the exact same time without making error, maybe I will need to do so later.

[Ali.Kourani]

Hi, 
I read the above thread, I am facing the exact point you pointed at. I am controlling 3 different USRPs from the same Host code each with different bitfile. In the host code I need to use different FPGA references at the same time. I am getting the error -61202. One of the devices is only runs at once ( i think this means one refernce was opened and run) while others fail for that based on the probes i set to monitor errors.
Any idea how to use different FPGA references at the same time in the code??  

[Terry_ALE]

Generally speaking host code should be designed using a software architecture.  Some projects are built bottom up and the host code tends to be an after-thought.  When you have more than one device this becomes even more critical.  Don't mean to be presumptuous about your case but if this happened in your case then it becomes difficult to work with.

Questions: can you run one or just two devices at a time?  How coupled is the host code as it interfaces with the three devices?

[Ali.Kourani]

Hi Terry,
I am using LabView Communication Design Suite 2.0. I was able to run 3 devices at the same time: 1 acting as a receiver and 2 acting as transmitters. BUT I have been using the same Streaming XCVR code (thus same bitfile) on all all devices (this FPGA code was containg a transmission section addressing TX output ports and a receiver section adressing recepton ports so thats why it was oke to run same code on differnet USRPs and have them operate differently). I did not need to open FPGA references for different bitfiles.

Through the HOST code previously I only needed to open FPGA references referenced to same bitfile for all devices under control.

Currently I need to pass different FPGA codes (different Streaming XCVR codes each establishing different transmission scheme) thus different bitfiles to pass to each device separately. So I built the different bitfiles and passed each one to the corresponding FPGA reference of the corresponding targeted device in the HOST code.

Sometimes reception starts successfully., some other trials only TX1 device starts, others TX2. but never did both TXs work at the same time. The error code was -61202 stating failure in opening FPGA ref. I set probes over the code in different locations to localize the error. It was always in the same place, where FPGA ref for each device are to be opened. I read some info online that I could use different FPGA ref with different bitfiles controlling same target but not at the same time, but this was not my case. I want to use different FPGA ref with different bitfiles each associated with a target device at the same time. 

Thinking aloud: " if it is not possible to do such scheme then how did it happen to one of the transmitter devices and the receiver to work instantly (while the third failed to open FPGA ref because of other refs. is open) and each one is referenced with separate different FPGA ref and bitfile"


some errors I have seen: error in " Open FPGA reference VI' -61202
error in "Run FPGA reference VI"(error -61003)
Tried rebooting devices, Host PC, using other devices...
I apologize for the long message, I was trying to describe the problem.

[Ali.Kourani]

Sorry forgot to add: coupling is done using CPS-8910 bridge and using PXIe x4 connectors and the host PC is connected to bridge with NI ExpressCard

[Terry_ALE]

There could be a race condition in your host code.