LabVIEW
How to synchronize four sessions on three 6561 cards?
I am trying to synchronize two generation channels on different HSDIO devices using TClk, and the channel to channel time delay is not tight enough for my application. Is there any way that I can improve this channel to channel time delay?
If having two channels synchronized at this time delay is not tight enough, it is possible to take advantage of the features such as data position delay and adjust sample clock relative delay to improve channel to channel synchronicity. Data Position Delay allows you to shift the position of your generation data relative to the sample clock, while the Adjust Sample Clock Relative Delay allows you to adjust the sample clock relative to the reference clock. When externally clocking your generation, use the data position delay feature. When using the onboard internal clocks, use the adjust sample clock relative delay vi. For more information on Data Position Delay, please see the addendum at the bottom of the page (taken from Digital Waveform Generator / Analyzer Help)
External Clocking
If you are using external clocking on your HSDIO devices and wish to synchronize two channels on two boards, follow the basic programming flow as follows:
- Configure both HSDIO devices for generation
- Synchronize devices using TClk
- Generate identical data on both devices
- Use a high sampling rate oscilloscope (e.g. NI 5114) to monitor time delay between identical channels on both devices. (The easiest method would be to use the Scope Soft Front Panel and view the time delay measurement)
- If one device lags the other, increase the data delay of the other device until the time delay is minimized
One caveat is that while this method can synchronize two channels on different devices, channel to channel delay on the same board must still be accounted for. Therefore, while you may be able to synchronize channel 0 of device 1 and channel 0 of device 2 to this resolution, this does not guarantee that channel 1’s of these devices will also be synchronized to this level.
Attached is some LabVIEW code that demonstrates this principle. Two HSDIO devices share a 100 MHz external clock, and generate the same HWS test pattern. The hardware setup is shown in an attached JPG file.
Internal Clocking
If you are using the internal clock on your HSDIO devices and wish to synchronize them, you can also use the Sample Clock Delay on the NI-TClk property node to align the sample clock of one device with the sample clock of another. This property allows you to align the sample clocks on synchronized devices. It is also worth noting that the sample clock delay is only adjustable for generation sessions only.
Data Position Delay Resolution
NI digital waveform generator/analyzers have three internal independent delay mechanisms, one for dynamic generation, one for dynamic acquisition, and one for the exported Sample clock. The delay mechanisms are capable of delaying the data and clock positions by up to one full Sample clock period, for Sample clock frequencies of 25 MHz and above. Refer to the specifications document for your device for valid frequencies and ranges for delays.
