Importing a Xilinx ISE Schematic to LabVIEW FPGA

[Akello]

Hello all, 

What I am trying to accomplish is a combination of Xilinx 12.4 ISE and LabVIEW FPGA. Initially, I just want to define the Digital Logic in a Xilinx ISE schematic and import that into my LabVIEW FPGA VI where I add the inputs and outputs. Later, I would like to expand to something more complicated where part of the Digital Logic is defined in Xilinx ISE and part in LabVIEW FPGA but for now I am just trying to verify that this is possible. 

I found a video tutorial on how to accomplish what I am saying from HDL to LabVIEW FPGA:

http://www.youtube.com/watch?feature=player_embedded&v=rJq4kag4Gx8

but have so far been unsuccessful in locating anything on how to do this with a schematic. The reason for my search is that I do not know any HDLs, I use the schematics in ISE, and while I could follow the instructions in the video for something simple, troubleshooting would be impossible for higher complexity.

Do anyone have any experience importing ISE schematics into LabVIEW? It would really help me out.

Thanks,

Yusif Nurizade

[T-REX$]

You will not be able to import the schematic file directly into LabVIEW FPGA. If you build your schematic into an .ngc file, you can use either CLIP or the IP integration node to bring your IP into LabVIEW.

I honestly do not know exactly what is required to build a Xilinx ISE Schematic file into an .ngc, so I won't be able to help you with that part of the process...

[Akello]

Thanks for the response T-REX, I've been reading the link you sent me and trying to figure out what to do. I also had some followup questions I was hoping you could help me with.

My problem with the CLIP is that it requires knowledge of HDL which I do not have. I mentioned in the orignal post that I found a video that explained how to create a Digital Logic component in LabVIEW using HDL code. The problem is while I could follow this for something simple, I am working on something more complex that would be too hard to troubleshoot if I went through in this manner.

I found a promising link in the one you sent me:

http://www.ni.com/white-paper/12918/en 

If I understand correctly, it is saying that I can use Xilinx Core Generator to create premade digital logic elements from an available list. That might work better in terms of allowing me to recreate the schematic without having to build every element myself. The issue I am having is I do not quite understand how to use the Xilinx Core Generator in LabVIEW. The link says that it should be part of the FPGA module and that I can access it via Programming»Xilinx Coregen IP»Math Functions»Floating-point but I have nothing of the sort. The closest thing that I have in my Programming Tab is an IP Integration option that has me selecting among files when it opens. I'm curious if there is an add-on I should be downloading or what else the problem could be. Should I start a new thread of this?

Finally, I recall seeing something about using Multi-SIM to create schematics that could be transferred to LabVIEW. Is this a viable option or would Multi-SIM be outside the scope needed for a recreation of a XILINX ISE Schematic?

Thanks,

Yusif Nurizade

[WesWNI]

Hello Akello,

The Xilinx CORE Generator IP palette will be installed with the Xilinx Compile Tools (13.4 will be the compatible version for LabVIEW 2012) linked below. Unfortunately, I cannot comment as to if the use of Multisim is a viable means of recreating the Xilinx ISE Schematic however, I believe the use of a CLIP or the Digital Logic components would be preferable. 

https://www.ni.com/en/support/downloads/software-products/download.labview-fpga-compilation-tool.htm... (LabVIEW 2012 FPGA Module Xilinx Tools 13.4)

https://www.ni.com/en/support/documentation/compatibility/19/compatibility-between-xilinx-compilatio... (Which Xilinx Compile Tools Do I Need to Compile My FPGA Code?)

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YHE3CAO&l=en-US (Export Digital Logic to Xilinx FPGAs With NI Multisim)

[Akello]

Wes,

Thank you very much for the response. I am almost afraid to ask because I fear I know the answer but is the Xilinx Core Generator IP Pallette available for the 12.4 Version that runs on LabVIEW 2011 SP1?

It does seem that the way this will ultimately be accomplished is either using the Coregen or creating everything from scratch. We were hoping that it would be possible to import directly from the schematic but our plan will have to be adjusted.

Thanks again,

Yusif

[T-REX$]

Hey Yusif,

The Xilinx Core generator was introduced to LabVIEW by NI Labs in 2010. It shipped with the LabVIEW 2011 FPGA Module by default. What target are you compiling for? It may just be that your target does not support CoreGen IP.

LabVIEW 2011 SP1 with Xilinx Compile Tools 12.4 has "Xilinx Coregen IP" added to the programming palette for Virtex-5 and Spartan-6 targets, Virtex-II and Spartan-3 Targets are not supported.

You can test this yourself by adding a Virtex-5 target (7854R is a good one) to your project. Remember, you don't actually need the target to test/compile for it. Just select the "New target or device" option from the "New->Targets and Devices" dialogue window.

 - TJ

[Akello]

TJ,

Thank you for your response. I apologize for my late replies; I am in NYC right now and we've all feeling the impact of the hurricane.

Though I do not have the board available right now, I am fairly certain it is the Digital Electronics FPGA which I believe is a Spartan-3E. Does this mean that the Core generator is not supported? Should I still try the target addition?

Thanks again for the help,

Yusif

[BradM]

The issue you might run into is that the Core Generator may try to target some features of the FPGA fabric which are not present in the Spartan 3E fabric, but the easiest way to check would be to attempt to generate code, insert it into a CLIP, and check to see if the compilation complains about instantiating something that is not supported on that device

[Akello]

Everyone,

Thank you for the advice, it has been really helpful in shaping how the project will proceed.

After speaking to my professor, the decision has been made to go ahead with importing HDL code into the LabVIEW FPGA using the IP Interface Node.

I will be starting small; 2 bit 2-to-1 MUX to 2-to-4 Decoder and work my way out from there. Hopefully importing the HDL will not give me too much trouble.

Thanks again,

Yusif Nurizade

[BradM]

If you have any difficulty getting that working, don't hesitate to stop back and ask some questions, however there's some great documentation to be found online and installed with LVFPGA as well aiding in the use of the IPNode, including the improvements to importing. If your design calls for synchronous logic within the IP that's imported into the LVFPGA diagram, make sure to look at how to express IO as clocks as there are some additinoal checks that the LVFPGA code will do if you note that a signal is to be used as a clock