Improving scanned IO read/write performance

[psears]

I have a cRIO 9074 which I am using as an EtherCAT master. So far I have been unsuccessful in attaining the benchmarks published by NI at https://www.ni.com/en/support/documentation/supplemental/08/ni-scan-engine-performance.html .

I have 7 3rd-party EtherCAT slave devices each with 4 read channels (24 bytes) and 4 write channels (24 bytes) for a total of 336 bytes each cycle. I open a shared variable reference once before executing my loop as described here https://www.ni.com/docs/en-US/bundle/labview/page/reading-and-writing-shared-variables-programmatica... .

I've also removed all software from the cRIO except for critical components such as Industrial Communication for Ethercat, and RT. I've removed all controls and indicators from my front panel and have tried deploying my code as a startup exe. Despite these efforts, the best performance I've been able to achieve is a scan engine period of 4ms which brings the CPU load up to 84%. Ideally I'd like to hit 500 Hz and have some margin available on the CPU.

From other posts such as https://forums.ni.com/t5/LabVIEW/crio-cpu-load/m-p/2623575/highlight/true#M785652 it seems like I should be able to achieve much better performance. Do I need to go to a different architecture such as direct IO access or a custom FPGA instead of the scan engine? Is this even possible using a 3rd party slave like I have?

[christian_w]

from the white paper 7792

...

It is important to note that these benchmarks are taken with the I/O variable error clusters wired together. Due to details of the LabVIEW compiler, the I/O variable nodes execute two to three times faster when executed sequentially.

I/O variable nodes execute faster using scanned access mode than direct access mode.

...

- use network streams instead of shared variables 

- write your own FPGA vi is also a good idea (use DMA FIFO's between FPGA and RT)