Actually with LabVIEW FPGA 1.1 (for LabVIEW 7.1) it is now possible to integrate your own VHDL code with the LabVIEW FPGA code. The new HDL node allows you to add the VHDL and interface it to the LabVIEW diagram.
LabVIEW FPGA 1.1 also includes a number of new analysis and processing functions including PID as well as discrete control and simulation routines.
Built-in FIFO functions provide access to 80kb of memory for easy-to-use FIFO functionality within your LabVIEW FPGA application.
The new single-cycle while loop increase processing speeds and can execute multiple functions in a single clock cycle of the FPGA which help in developing high-speed interfaces with DIO, clock/trigger lines, and RAM.
LabV
IEW 7.1Christian L
NI Consulting Services
authored byChristian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX

