Issue with phase locked loop instability

[Ringding]

I've written a piece of code to process data stored in a TDMS file with a lock in amplifier.  After some head scratching I am getting sensible outputs from the amplifier but I'm not achieving the sort of performance I was hoping for. 

The data is being recorded from an automated test utility that raster scans a modulated source (constant at 800Hz) across the field of view of a piece of optical lab equipment.   

Monitoring the fr output from the PLL shows that it is not consistently calculating the reference frequency correctly.  It sometimes drops to 730Hz from 800Hz.  I think this is causing 'noisy' results.  To give an indication of the effect this is having on my data I've attached the raw data from one run, as well as the data once it has been passed through the LIA.  It can be seen that the signal intermittently drops right down (I think these points correspond with drop in frequency). 

I'm capturing the signals at 250kS/s and the signal at each mirror position is 5000 samples long i.e. 0.02s or 16 cycles.  I would expect this to be a large enough sample to accurately measure the reference signal.

I've also attached a screen grab of the LIA setup.

Any pointers on how the staibility of the PLL could be improved would be appreciated.

thanks.

[Ringding]

Just bumping this to the top!

I've had no luck resolving this issue and might have to accept using the raw data for now if I can't find a way around this.

Is there a minimum number of cycles of reference required by the PLL to be able to read the reference frequency?  Is 16 cycles too few?

Thanks.

[Ringding]

BTT

[johnsold]

I have not used the lock in amplifier or PLL VIs but I have worked with hardware PLLs quite a bit.  The time to lock (or number of cycles) for a PLL depends in complicated ways on the signal to noise ratio, the filters, the initial phase and frequency differences, the type of phase detector used, and probably the phase of the moon.  Sixteen cycles might be long enough if the initial frequency and phase is close.  Some RF PLLs take milliseconds to lock when the frequency is in the tens or hundreds of MHz - thousands of cycles.

If the frequency does not drift much from one mirror position to the next, holding the frequency and using that as the starting point for the next position might help.  To obtain an initial lock, can you hold one position until it locks before starting to scan?

What happens to the signal while scanning? You mention raster scanning and "signal at mirror position." Is the scan continuous or does it move to a position and hold there for some time before moving to the next position?

Lynn 

[Ringding]

Thanks for the reply. 

The frequency stays very constant from one mirror position to the next.  The scan is not continuous, the mirror is moved to a position, held for a period of time, and the moved to the next position etc.  The data I am processing has already been captured in TDMS files and I am post-processing it.  Unfortunately I do not have the time, nor money (as always!), to repeat the experiments with a longer duration at each mirror position.

I take your point about the number of factors that impact on the time to lock, it wouldn't suprise me at all if the lunar cycle was somehow involved as well!

I'm not sure on how the NI PLL module locks in and am considering putting together my own LIA design.  Taking your idea of a longer dwell at the start position (which I can't do) perhaps, as the reference frequency does not vary, I can somehow configure a bespoke PLL that starts at the nominal reference frequency? 

I too have used hardware LIA's plenty of times, but had never really stopped to consider how they operate.  Now that I'm trying to get one to work in software I'm finding it intriguing, if frustrating.

Thanks for your input, any other suggestions gratefully received.

[johnsold]

Do you know if the phase is continuous across mirror positions?  In other words, if you were locked at position i and did not change the frequency or phase while moving to position i+1, would the signal from position i+1 be in phase with the original signal?

How do you know when you are moving and when you are in position? I did not see anything which appeared to pay attention to good or bad parts of the data.  Any phase discontinuity in the data stream can really mess up the PLL.

Lynn 

[Ringding]

I don't know.  I suspect any variation will be small if it exists.  Because of the nature of the optical system generating the signal there may be a small phase change (~20°) but I would have to analyse the signals to check.  It is an interesting point and I'll have a look.

The LabView routine that carries out the measurement moves to a position and then dwells for the necessary time to take the sample.

I'll have a look at if there is any discontinuity in the phase.

Thanks.

[Coq_Rouge]

Do you really need the PLL. Can you use the reference signal direct?

[Ringding]

That's an interesting idea.  I'm not sure how I would go about constructing the necessary input to the LabView LIA though.

Could you suggest how I might go about this please?

Failing that I'll try to make time to have a play in the lab this evening.

[Coq_Rouge]

A Lock-in amplifier is composed of a PLL and a phase sensitive detector. But in some cases the PLL is not needed. Is the reference you are using a good and pure sine wave? Is your measured signal derived from the reference signal but differs in phase and amplitude(noise is not a problem for this signal)? If the answer is yes to both I think you may skip the PLL part.

Which Labview version do you use, and what do you want as output from your "lock-in" app