LV FPGA 8.0 Compiler Bug (Error -61059)

[mysterj]

I believe I've uncovered a bug in the LV FPGA 8.0 compiler.

I have a FPGA VI  that includes a Conditional Disable structure with several controls inside.  This FPGA is interfaced to a host VI that runs on a RT target.  When these Conditional controls are disabled, the FPGA is compiled and then run from the host VI, I get the following error in the host VI:

    Error -61059 occurred at Read/Write Control: <control name> in <VI name>.
    Possible reason(s):
    LabVIEW FPGA:  (Hex 0xFFFF117D) The selected control was not found or is out of sync.

In troubleshooting the problem, I discovered that some of the the controls not inside the Conditional Disable Structure were missing from the FPGA bitfile, even though they are present in FPGA VI.  If the Conditional Disable structure is deleted and the VI recompiled, the problem is eliminated.

I've reported this problem to NI Support, but am posting it here so others may be aware of this problem.

[LabVU_Dog]

I'm having a similar problem. I have an indicator (cluster of 8 booleans, type-def'd) on the FPGA VI FP. After I compile the VI, it seems to run fine (I can test it from it's front panel). When I try to link to the FPGA VI from the RT host, I have no trouble. I can also get data via FIFO from the FPGA VI. But when I try to read the control, I get error -61059 on the RT host from the FPGA R/W Control node.

I do not have any conditional disable structure code.

Any ideas?

In the meantime, I'll try disconnecting the type def.

[LabVU_Dog]

I recompiled the FPGA VI after I un-linked the type def. I closed/saved it and opened the Host (RT) VI and ran it. No more problems.

It looks like the bug manifests itselft with type defs, too.

I'm running LV 8.2 on Win XP.

Workaround found.

[jdigiova]

The problem with using controls/indicators inside conditional disable structures has already been reported to NI and is fixed in version 8.2.  Here is a link to the KB.

http://digital.ni.com/public.nsf/websearch/D77E88D9B04BA71F862571760047FD98?OpenDocument

Regards,

Joseph D.

[LabVU_Dog]

Controls/Indicators in a conditional disable block was NOT the problem that I had.

My problem was that I could not read an indicator on the front panel of the FPGA VI that was type-def'd.

I worked around it by disconnecting the indicator from the type def.

[jdigiova]

My previous post was in response to mysterj's post, in which he was using conditional disable structures.  There are no reported issues on using typedefs on FPGA causing the host to not be in sync with the FPGA.  LabVU_Dog can you please provide code that reproduces this issue?  I created an FPGA VI with an indicator that was a typedef cluster of 8 booleans.  I was able to interact with the FPGA VI with no problems both in interactive mode and through the host interface.

Regards,

Joseph D. 

[Vladimir_Drzik]

Hello Joseph

I'm experiencing the same problem as LabVU_Dog. However, it seems to me that the typedefs make problems only if they are in a project library. Please have a look at my attached code. I'm using PCI-8254R.

Vladimir

[jdigiova]

Thank you for the example code.  I have reproduced the problem and will file it to R&D.

Regards,

Joseph D.