Hello there,
I’m in desperate need for your help since, once again, there is not proper documentation for the error I’m getting…
The error “explanation” says: «The IO module PLL did not lock to the provided reference in time. Please check your cable connections and system configuration and try again.»
The error occurred after the host PC hanged to keeping up with the computation of data transferred from the KU060 on a PXIe-5785 module
Edit: self test in NI MAX for the board passes.
Since then, no FPGA design is responding after the Open FPGA VI Reference (nor the dynamic one too) returning that -304316 error.
Restarted the windows host several times but did not work too.
Please help
