LabVIEW 2009 FPGA Module for Xilinx Spartan 3E Starter Board- Intel StrataFlash

[ThisIsSparta3e]

Hi,

I've been trying to read in bytes from the Intel StrataFlash using the framework of the examples provided; however, in order to read data from the StrataFlash, the FPGA's output buffers must be driven to a high impedance (SPI_MISO = 'Z', and SF_D[7:1] = "ZZZZZZZ").

Does the LabVIEW FPGA Module provide support for this kind of functionality?

Thanks,

Alfonso

[charris]

Hello Alfonso!

What hardware are you using to read from the data? Would you be willing to provide some more details of your system setup?

Judging by your initial post, are you attempting SPI communication using the DIO of your FPGA device?

[ThisIsSparta3e]

I'm trying to use an FPGA VI to read and write data to/from the Intel StrataFlash memory on the Spartan 3E board. The 7 most significant data bits are transferred via the Strata Flash Bus SF_D[7:1] while the least significant bit is transferred over the SPI bus SPI_MISO.

I've followed the Intel datasheet for the StrataFlash carefully, but I still can't get it to work. Since the Strata Flash Bus lines function as both inputs and outputs for the Spartan 3E board, I was trying to find a way to set them to high impedance while reading from the StrataFlash memory. Maybe some of the timing is wrong as well?

I'll refer you to a sample implementation posted by wedo. 

. 

[charris]

So, the impedance state of the 3E is going to be governed by the hardware. If it is supported, it is likely that this state corresponds to a specific digital line state. You may simply need to perform a DIO read or write to switch the line to the appropriate state, but I'm honestly not sure. If the capability exists, it will likely be an I/O item that can be called/accessed from the FPGA VI.

Have you posted this on the Xilinx Spartan Family forums? You may have better luck there, since there's a good chance this is a hardware question as much as a software one.

[ThisIsSparta3e]

I'll try that. Thanks!

Alfonso